CMS32L051 User Manual |Chapter 18 Interrupt Function
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Chapter 18 Interrupt Function
The Cortex-M0+ processor has a built-in Nested Vector Interrupt Controller (NVIC) that supports up to 32
interrupt request (IRQ) inputs, as well as one non-maskable interrupt (NMI) input, and multiple internal
exceptions.
The interrupt source for 32 interrupt request (IRQ) inputs and 1 non-maskable interrupt (NMI) input is
processed in this system. This user manual only describes the handling in this system, Cortex-M0+ processors
built-in NVIC functions, please refer to the Cortex-M0+ processor user manual.
18.1 Types of interrupt function
There are two types of interrupt functions.
(1) Interrupts can be masked
This is a shielded controlled interrupt. If the interrupt mask flag register is not open, the interrupt request
will not be responded to even if it is generated.
It can generate a standby release signal to cancel the deep sleep mode and sleep mode.
Masked interrupts are divided into external interrupt requests and internal interrupt requests.
(2) Interrupts cannot be masked
This is an unmasked interrupt that the CPU must respond to once the interrupt request is made.
18.2 Interrupt source and structure
Suspend source columns table reference Table 18-1.
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