Cmsemicon CMS32L051 - A;D Converter Trigger Mode Register (ADTRG)

V1.2.2
CMS32L051 User Manual |Chapter 11 A/D Converter
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11.2.5 A/D converter trigger mode register (ADTRG)
This is the register that sets the A/D conversion trigger mode and the hardware trigger signal.
The AD TRG register is set via an 8-bit memory operation command.
After the reset signal is generated, the value of this register becomes 00H.
Figure11-8 Format of A/D converter trigger mode register (ADTRG)
Reset value: 00H
R/W
7
6
5
4
3
2
1
0
ADTRG
ADTMD1
ADTMD0
0
0
0
0
ADTRS1
ADTRS0
ADTMD1
ADTMD0
Selection of A/D conversion trigger modes
0
0
Software triggering mode
0
1
1
0
Hardware triggers no-wait mode
1
1
The hardware triggers the wait mode
ADTRS1
ADTRS0
Selection of hardware trigger signals
0
0
The counting end of timer channel 1 or the capture of the end interrupt signal
(INTTM01).
0
1
The event signal selected by ELC
1
0
Real-time clock interrupt signal (INTRTC).
1
1
Interval timer interrupt signal (INTIT).
Note 1 To override the ADTRG register, it must be done in the transition stop state (ADCS=0, ADCE=0).
2. In order to end the A/D conversion normally, the hardware trigger interval must be set at least to the following time:
When hardware triggers no-wait mode: 2 f
CLK
clocks + A/D conversion time
When the hardware triggers the wait mode: 2 f
CLK
clock + A/D power supply stable wait time + A/D transition time
Note 1. f
CLK
: Clock frequency of the CPU/peripheral hardware