Cmsemicon CMS32L051 - Peripheral Enable Register 1 (PER1); DMA Control Register J(Dmacrj) (J=0~23)

V1.2.2
CMS32L051 User Manual |Chapter 16 Enhanced DMA
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16.3.4 Peripheral Enable Register 1 (PER1)
The PER1 register is a register that sets the clock that enable or disables clocking each peripheral
hardware. Reduce power consumption and noise by stopping clocking unused hardware.
To use DMA, bit3 (DMAEN) must be set to 1.
The PER1 register is set via an 8-bit memory operation command. After the reset signal is generated, the
value of this register becomes 00H.
Figure 16-5 Format of the peripheral enable register 1 (PER1).
Address: 4002081AH after reset: 00H R/W
symbol
PER1
DMAEN
Provides control of the input clock of the DMA
0
Stop supplying the input clock.
 cannot be run.
1
An input clock is provided.
 can run.
16.3.5 DMA control register j(DMACRj) (j=0~23).
The DMACRj register controls the operating mode of the DMA.
7
6
5
4
3
2
2
1
0
0
0
-
0
DButIn
0
0
0