Cmsemicon CMS32L051 - Page 584

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CMS32L051 User Manual |Chapter 16 Enhanced DMA
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Figure 16-6 Format of DMA control register j (DMACRj)
Address:
Refer to 16.3.2
Control data allocation
. A
fter reset: Indefinite value
R/W
Symbol:
15
14
13
12
11
10
9
8
DMACRj
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
S
RPTINT
CHNE
DAMOD
SAMOD
RPTSEL
MODE
S
Selection of transmitted data length
00
8
bits
01
16
bits
10
32-bit
11
Disable the setting
RPTINT
Repeating pattern interrupts allow/disable
0
Interrupts are prohibited.
1
Interrupts are allowed.
When the MODE bit is 0 (normal mode), the RPTINT bit is not set.
CHNE
Allow/disallow for chain transfers
0
Chain transmission is prohibited.
1
Allow chain transfer.
The CHNE bit of the DMACR23 register must be 0 (chain transfer is prohibited).
DAMOD
Control of the transmitting destination address
0
fixed
1
Increasing
When the MODE bit is 1 (repeat pattern) and the RPTSEL bit is 0 (the transfer target is the repeat
area), the DAMOD bit is not set.
SAMOD
Control of the transmitting source address
0
fixed
1
Increasing
When the MODE bit is 1 (repeat pattern) and the RPTSEL bit is 1 (the delivery source is the repeat
region), the SAMOD bit is not set.
RPTSEL
Selection of repeating areas
0
The delivery target is a repeating area.
1
The delivery source is a repeat.
When the MODE bit is 0 (normal mode), the setting of the RPTSEL bit is invalid.
MODE
Selection of transfer mode
0
Normal mode
1
Repeating pattern
Note DMACRj register cannot be accessed via DMA transfer.