Cmsemicon CMS32L051 - Extension Code

V1.2.2
CMS32L051 User Manual |Chapter 14 Serial interface IICA
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14.5.11 Extension code
(1) When the high 4 bits of the receive address are 0000 or 1111, as the extension code is received,
the extension code receive flag (EXCn) is set to 1, and in the 8th The falling edge of the clocks generates an
interrupt request (INTIICAn).
Does not affect the local station address saved in the slave address register n (SVAn).
(2) When the setting value of the SVAn register is 11110xx0, if 11110xx0 is sent from the master
device through a 10-bit address, the following assertions occur. However, an interrupt request (INTIICAn) is
generated on the falling edge of the 8th clock.
 High 4 bits data are the same: EXCn=1
 7 bits of data are the same: COIn=1
Note EXCn: bit5 of the IICA status register n (IICSn).
COIn: bit4 of IICA status register n (IICSn).
(3) The processing after the interrupt request occurs differs depending on the subsequent data of the
extension code, which is processed by software. If the extension code is received while the slave is running, it
is participating in the communication even if the address is different. For example, if you do not want to
operate as a slave after receiving an extension code, you must set bit 6 (LRELn) of IICA control register n0
(IICCTLn0) to "1" to enter the standby state for the next communication.
Table 14-3 Bit definitions of major extension codes
Slave address
R/W bit
Illustrate
0000000
0
Full call address
11110xx
0
Specification of a 10-bit slave address (when the address is authenticated).
11110xx
1
The designation of a 10-bit slave address (when a read command is issued
after the address is identical).
Note 1. For extensions other than those listed above, please refer to the I
2
C-bus datasheet issued by NXP Corporation.
2.n=0