Cmsemicon CMS32L051 - Chapter 4 Clock Generation Circuit; 4.1 Function of the clock generation circuit

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CMS32L051 User Manual |Chapter 4 Clock Generation Circuit
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Chapter 4 Clock Generation Circuit
The presence or absence of resonator connection pins for master system clock/external clock input pins,
resonator connection pins for subsystem clocks/external clock input pins varies depending on the product.
4.1 Function of the clock generation circuit
A clock generation circuit is a circuit that generates a clock to the CPU and peripheral hardware. There
are three types of system clock and clock oscillation circuitry.
(1) Main system clock
① X1 oscillation circuit
The clock from f = 1 to 20MHz can be oscillated by connecting a resonator to the X1 and
X2
pins, and it can be used to enter deep sleep mode or set MSTOP the bit (bit7 of the clock
operating state control register (CSC)) stops the oscillation.
② High-speed internal oscillator (high-speed OCO)
Can be used from fHOCO=64MHz, 48MHz, 32MHz, 24MHz, via option byte (000C2H). 16MHz,
12MHz, 8MHz, 6MHz, 4MHz, 3MHz and 2MHz (TYP) selects the frequency for oscillation. After
the reset is released, the CPU must start running with this high-speed internal oscillator clock.
Oscillation can be stopped by entering deep sleep mode or setting the HIOSTOP bit (bit0 of the
CSC register). The frequency of the option byte setting can be changed through the frequency
selection register (HOCODIV) of the high-speed internal oscillator. For frequency settings, refer
to Figure 4-10 Format of .
In addition, an external master system clock (fEX = 1 to 20MHz) can be provided by the EXCLK/X2/P122
pin and the input to the external master system clock can be disabled by entering deep sleep mode or by
setting the MSTOP bit.
Switching between high-speed system clock (X1 clock or external master system clock) and high-speed
internal oscillator clock can be performed by setting the MCM0 bit (bit4 of the system clock control register
(CKC)).
(2) Subsystem clock
① XT1 oscillation circuit
The clock of fXT=32.768kHz can be oscillated by connecting a 32.768kHz resonator to the XT1
pin and XT2 pin, and the XTSTOP bit (clock operating status control register (CSC) bit6) to stop
the oscillation.
In addition, an external subsystem clock (f
EXS
=32.768kHz) can be provided by EXCLKS/XT2/P1 pin 24,
and the input of the external subsystem clock can be invalidated by setting the XTSTOP bit.