Cmsemicon CMS32L051 - Timer Output Mode Register M (Tomm)

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CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4)
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5.3.12 Timer output mode register m (TOMm)
The TOMm register is a register that controls the output mode of each channel timer. When used as
a standalone channel operation function, the corresponding position of the channel used is 0.
When used as a multi-channel linkage operation function (PWM output, single-trigger pulse output,
and multiple PWM output), the corresponding position of the master channel is 0 and the
corresponding position of the slave channel is 1.
When the timer output (TOEmn=1) is allowed, the setting of each channel n of the timer output
signal is reflected in the timing of the set and reset of the output signal of this register.
The TOMm register is set via a 16-bit memory operation command.
I can set the low 8 bits of the TOMm register with TOMmL and via an 8-bit memory operation
command. After the reset signal is generated, the value of the TOMm register changes to 0000H.
Figure 5-21 Table of timer output mode register m (TOMm)
Symbol
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TOMm
TOMmn
Control of the timer output mode of channel n
0
The main channel output mode (alternately output via timer interrupt request signal (INTTMmn).
1
Slave channel output mode (the output is asserted via the timer interrupt request signal
(INTTMmn) of the master channel and reset by the timer interrupt request signal (INTTMmp) of
the slave channel).
Note: bit15 to 4 and bit0 must be set to 0.
Remark: m: Unit number (m=0,1) n: channel number n=0~3 (for the main channel: n=0, 2 )
p: The slave channel
number
n=0：p=1, 2, 3
n=2：p=3
(For more information on the relationship between master and slave channels, refer to 5 4.1 Basic rules for
multi-channel linkage operation function).
0
0
0
0
0
0
0
0
0
0
0
0
TOM
m3
TOM
m2
TOM
m1
0