CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4)
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5.3.2 Timer clock select register m (TPSm)
TPSm register is a 16-bit register that selects 2 or 4 common operating clocks (CKm0, CKm1, CKm2)
available to each channel, CKm3). CKm0 is selected by bits 3 to 0 of the TPSm register, and CKm1 is selected
by bits 7 to 4 of the TPSm register. In addition, only channel 1 and channel 3 can select CKm2 and CKm3.
CKm2 is selected through bits 9 to 8 of the TPSm register, and CKm3 is selected through bits 13 and 12 of the
TPSm register.
The TPSm register in timer operation can only be overridden in the following cases.
In the case where PRSm00~PRSm03 bits can be rewritten (n=0~3):
Select CKm0 as the running clock (CKSmn1, CKSmn0=0, 0) for all channels in the stopped state
(TEmn=0).
In the case where PRSm10~PRSm13 bits can be rewritten (n=0~3):
Select CKm2 as the running clock (CKSmn1, CKSmn0=0, 1) for all channels in the stopped state
(TEmn=0).
Can override the PRSm 20 bits and PRSm 21 bits (n=1, 3):
Select CKm1 as the channel running clock (CKSmn1, CKSmn0=1, 0) all in the stopped state (TEmn=0).
Can override PRSm 30 bits and PRSm 31 bits (n=1, 3):
Select CKm3 as the running clock (CKSmn1, CKSmn0=1, 1) for all channels in the stopped state
(TEmn=0).
The TPSm register is set via 16-bit memory operation instructions. After the reset signal is generated, the
value of the TPSm register changes to 0000H.
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