Cmsemicon CMS32L051 - Page 122

V1.2.2
CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4)
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Figure 5-7 Format of the timer clock selection register m (TPSm)(1/2)
Symbol
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TPSm
PRSmk3
PRSmk2
PRSmk1
PRSmk0
Selection of the running clock (CKmk)
Note
(k=0, 1)
0
0
0
0
f
CLK
0
0
0
1
f
CLK
/2
0
0
1
0
f
CLK
/2
2
0
0
1
1
f
CLK
/2
3
0
1
0
0
f
CLK
/2
4
0
1
0
1
f
CLK
/2
5
0
1
1
0
f
CLK
/2
6
0
1
1
1
f
CLK
/2
7
1
0
0
0
f
CLK
/2
8
1
0
0
1
f
CLK
/2
9
1
0
1
0
f
CLK
/2
10
1
0
1
1
f
CLK
/2
11
1
1
0
0
f
CLK
/2
12
1
1
0
1
f
CLK
/2
13
1
1
1
0
f
CLK
/2
14
1
1
1
1
f
CLK
/2
15
Note that in case of changing the clock selected as f
CLK
(changing the value of the system clock control register (CKC)),
the general-purpose timer unit (TTm=000FH) must be stopped. Even when selecting the operating clock (f
MCK
) or
the active edge of the input signal at the TImn pin, the general-purpose timer unit needs to be stopped.
Note 1 You must set bit15, 14, 11, and 10 to 0.
2. If you select f
CLK
(divided) as the running clock (CKmk) and set TDRmn to 0000H (m=0 , 1, n = 0 ~ 3), you can
not use the universal timer unit interrupt request.
Note 1. f
CLK
: The clock frequency of the CPU/peripheral hardware.
2. The TPSm register selects a clock waveform that is only 1 fCLK cycle high from the rising edge. For details,
please refer to 5.5.1 Counting Clock (fTCLK).
0
0
PRS
m31
PRS
m30
0
0
PRS
m21
PRS
m20
PRS
m13
PRS
m12
PRS
m11
PRS
m10
PRS
m03
PRS
m02
PRS
m01
PRS
m00