Cmsemicon CMS32L051 - Peripheral Enable Register 1 (PER1); EPWM Input Source Selection Register (EPWMSRC); EPWM Output Control Register (EPWMCTL)

V1.2.2
CMS32L051 User Manual |Chapter 6 Function of EPWM Output Control Circuit
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6.2.1 Peripheral enable register 1 (PER1).
The PER1 register is a register that sets the clock that allows or disables clocking each peripheral
hardware.
Reduce power consumption and noise by stopping clocking unused hardware.
To use the EPWM function, EPWMEN must be set to 1.
See 4.3.6 Peripheral Permissible Registers 0, 1 (PER0, PER1) for details
6.2.2 EPWM input source selection register (EPWMSRC)
The EPWMSRC register selects the source clock of the input clock of the real-time output circuit. Select
Timer's timer output TO01 or TO03 as the source clock and input to the EPWM.
The EPWMSRC register is set via an 8-bit memory operation command.
By generating a reset signal, the value of this register becomes 00H.
Figure 6-2 Format of EPWM input source selection register
Address: 0x40044400
After reset: 00H
R/W
symbol
7
6
5
4
3
2
1
0
EPWMSRC
SRC07
SRC06
SRC05
SRC04
SRC03
SRC02
SRC01
SRC00
SRC0n
Select the source clock for the EPWM0n output
0
Select TO01
1
Select TO03
Note n: Channel number (n=0~7).
6.2.3 EPWM output control register (EPWMCTL)
The EPWMCTL register performs allowable control and reverse control of the waveform output of
EPWMO00 to EPWMO03.
The EPWMCTL registers are set via 16-bit memory operation instructions.
After the reset signal is generated, the value of this register becomes 00H.
Figure 6-3 Format of EPWM Output Control Register (EPWMCTL).
Address: 0x40044408
After reset:
0000H
R/
W
symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
EPWMCTL
IE07
IE06
IE05
IE04
IE03
IE02
IE01
IE00
OE07
OE06
OE05
OE04
OE03
OE02
OE01
OE00
OE0n
Control of EPWMO0n output
0
Disable output
1
Enable output
Note n: Channel number (n=0~7).
IE0n
Reverse control of EPWMO0n output
0
Not reversed
1
Reversed
Note n: Channel number (n=0~7).