Cmsemicon CMS32L051 - A;D Converter Mode Register 2 (ADM2)

V1.2.2
CMS32L051 User Manual |Chapter 11 A/D Converter
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11.2.4 A/D converter mode register 2 (ADM2)
The ADM2 register is set by 8-bit memory operation instructions.
After the reset signal is generated, the value of this register becomes 00H.
Figure11-6 Format of A/D converter mode register 2 (ADM2) (1/3)
Reset value: 00H
R/W
7
6
5
4
3
2
1
0
ADM2
ADREFP1
HOMEP0
0
0
ADRCK
0
CHRDE
0
ADREFP1
ADREFP0
Selection of positive (+) voltage references for A/D converters
0
0
Provided by
V DD
.
1
0
Provided by internal reference voltage (1.45V).
other
Set Prohibited
ADRCK
Check the upper and lower values of the conversion result
0
When the ADLL the ADCR  ADUL register (AREA1), an interrupt signal
(INTAD) is generated.
1
When ADCRRegister <ADLLRegisters (AREA2OrADULTSRegister <ADCRRegisters
(AREA3), an interrupt signal is generated(INTAD).
The range of interrupt signal (INTAD) generated from AREA1 to AREA3 is shown in Figure 15-8.
CHRDE
The output of the channel identification is enabled when the A/D converter scans mode
0
When scanning mode, the channel number is not identified in the conversion results
1
When scanning mode, the high four bits of the converted result ([15:12] of the ADCR register)
are the channel numbers for this result
Figure11-7 Range of interrupt signal generation for the ADRCK bit
value in ADCR register
(A/D conversion result)
when ADRCK=1, generates
INTAD interrupt
when ADRCK=0, generates
INTAD interrupt
when ADRCK=1, generates
INTAD interrupt
configure value of ADUL register
configure value of ADLL register
Note 1 To override the ADM2 register, it must be done in the transition stop state (ADCS=0).
Note When INTAD does not occur, the A/D conversion results are not saved to the ADCR register and the ADCRH
register.