Cmsemicon CMS32L051 - One-Time Operation of the Tomn Bit

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CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4)
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Multiple TO0n outputs
can change
simultaneously
When the value is not
changed, the output
does not change
When the TOE0n bit is
"1", the write operation of
the TO 0n bit is ignored
5.6.4 One-time operation of the TOmn bit
Like the timer channel start register m (TSm), the timer output register m (TOm) has the set bit
(TOmn) for all channels. This allows the TOmn bit of all channels to be operated at once.
Figure 5-37 Example of a one-time operation with the TO0n bit
Before writing
TO0
TOE0
The data to write
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
After writing
TO0
Only the TOmn bit with TOEmn bit 0 can be written, ignoring the write operation of the TOmn bit with
TOEmn bit 1.
TOmn (channel output) with TOEmn bit 1 is not affected by write operations, even if the write
TOmn bit is ignored, and output changes caused by timer operation occur normally.
Figure 5-38 TO0n pin status when the TO0n bit is operated at one time
TO03
TO02
TO01
TO00
Before writing Write TO0n bit
Note m: unit number (m=0,1) n: channel number (n=0~3).
0
0
0
0
0
0
0
0
0
0
0
0
TO03
1
TO02
0
TO01
1
TO00
0
0
0
0
0
0
0
0
0
0
0
0
0
TOE03
0
TOE02
0
TOE01
0
TOE00
1
0
0
0
0
0
0
0
0
0
0
0
0
TO03
0
TO02
1
TO01
1
TO00
0