Cmsemicon CMS32L051 - 15.4 Considerations when using IrDA

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CMS32L051 User Manual |Chapter 15 IrDA
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15.3.4 High level pulse width selection
If the pulse width at the time of transmission is less than the bit rate x 3/16, the applicable IRCKS2
~ IRCKS0 bit setting (minimum pulse width) and the high-level pulse width at the time of setting are
shown in Table 15-2.
Table 15-2 IRCKS2 ~ IRCKS0 bits
fCLK
[MHz]
project
<Upper> Bit Rate [kbps]
<Lower >Bit Rate x 3/16[us]
2.4
9.6
19.2
38.4
57.6
115.2
78.13
19.53
9.77
4.87
3.26
1.63
1
IRCKS2~IRCKS0
001
001
001
- Note 1
- Note 1
- Note 1
High level pulse
].
2.00
2.00
2.00
- Note 1
- Note 1
- Note 1
2
IRCKS2~IRCKS0
010
010
010
010
010
- Note 1
High level pulse
].
2.00
2.00
2.00
2.00
2.00
- Note 1
3
IRCKS2~IRCKS0
011
011
011
011
011
- Note 1
High level pulse
].
2.67
2.67
2.67
2.67
2.67
- Note 1
4
IRCKS2~IRCKS0
011
011
011
011
011
000
Note 2
High level pulse
].
2.00
2.00
2.00
2.00
2.00
1.50
6
IRCKS2~IRCKS0
100
100
100
100
100
000
Note 2
High level pulse
].
2.67
2.67
2.67
2.67
2.67
1.50
8
IRCKS2~IRCKS0
100
100
100
100
100
000
Note 2
High level pulse
].
2.00
2.00
2.00
2.00
2.00
1.50
12
IRCKS2~IRCKS0
101
101
101
101
101
000
Note 2
High level pulse
].
2.67
2.67
2.67
2.67
2.67
1.50
16
IRCKS2~IRCKS0
101
101
101
101
101
000
Note 2
High level pulse
].
2.00
2.00
2.00
2.00
2.00
1.50
24
IRCKS2~IRCKS0
110
110
110
110
110
000
Note 2
High level pulse
].
2.67
2.67
2.67
2.67
2.67
1.50
Note 1. - indicates that the communication standard is not met.
2. The pulse width cannot be less than the bit rate 3/16.
15.4 Considerations when using IrDA
1. The operating clock of the IrDA can enable or disable by a peripheral enable register setting. The
initial state is to disable the supply of clocks, so the registers cannot be accessed. Before the registers can be
set, the peripheral allow registers must be set to allow the state of the IrDA operating clock to be provided.
2. In sleep mode, the IrDA function is continuously operated.
3. During IrDA communication, the initialization function of SCI (SS bit = 1) is prohibited.
4. The IRRXINV bit, IRTXINV bit, and IRCKS [2:0] bit of the IRCR register can be set only when the
IRE bit is 0.