Cmsemicon CMS32L051 - Master Transmission and Reception

V1.2.2
CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit
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12.5.3 Master transmission and reception
The transmission and reception of the master refers to the operation of the output transmission clock
of this product and the transmission and reception of data with other devices.
Note It must be used within the scope of the peripheral functional characteristics that meet this condition and meet the
electrical characteristics (refer to the data sheet).
Remark m: Unit number (m=0, 1) n: Channel number (n=0~3)p: SSPI number (p=00, 01, 10, 11, 20, 21.) )
mn=00~03, 10~11
3-wire serial I/O
SSPI00
SSPI01
SSPI10
SSPI11
SSPI20
SSPI21
Object channel
SCI0
Channel 0
SCI0
Channel 1
SCI0
Channel 2
SCI0
Channel 3
SCI1
Channel 0
SCI1
Channel 1
The pin used
SCLK00,
SDI00,
SDO00
SCLK01,
SDI01,
SDO01
SCLK10,
SDI10,
SDO10
SCLK11,
SDI11,
SDO11
SCLK20,
SDI20,
SDO20
SCLK21,
SDI21,
SDO21
interrupt
INTSSPI00
INTSSPI01
INTSSPI10
INTSSPI11
INTSSPI20
INTSSPI21
You can choose between an end-of-the-transmission interrupt (single-pass mode) or a
buffer null interrupt (continuous transfer mode).
Error detection
flag
Only the overflow error detection flag (OVFmn).
The length of the
transmitted data
7 or 8 bits
Transfer Rate
Note
Max. f
CLK
/2[Hz](Only.)SSPI00),f
CLK
/4[Hz]
Mi n.f
CLK
/(2 × 2
15
× 128)[Hz]f
CLK
: System clock frequency
Data phase
It can be selected via the DAPmn bit of the SCRmn register.
DAPmn=0: Data output starts when the serial clock starts running.
DAPmn=1: Starts data output half a clock before the serial clock starts running.
Clock phase
It can be selected by the CKPmn bit of the SCRmn register.
 CKPmn=0: Positive phase
 CKPmn=1: Inverted phase
Data direction
MSB preferred or LSB preferred