Cmsemicon CMS32L051 - 10.3 Registers for controlling watchdog timer

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CMS32L051 User Manual |Chapter 10 Watchdog Timer
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10.3 Registers for controlling watchdog timer
Control the watchdog timer through the watchdog timer enable register (WDTE).
10.3.1 Watchdog timer enable register (WDTE)
By writing ACH to the WDTE register, clear the counter for the watchdog timer and restart the count.
The WDTE registers are set via 8-bit memory operation instructions. After the reset signal is generated, the
value of this register changes to 9AH or 1AH
Note
.
Figure 10-2 Format of watchdog timer enable register (WDTE)
Address: 0x40021001 After reset: 9AH/1AH
Note
R/W
Symbol
7 6 5 4 3 2 1 0
WDTE
Note The reset value of the WDTE register varies depending on the setting value of the WDTON bit of the option byte
(000C0H). To make the watchdog timer run, you must set the WDTON bit set to 1.
Config value of the WDTON bit
Reset value of the WDTE register
0 (disable the counting run of the watchdog timer).
1AH
1 (enable the counting of watchdog timers to run).
9AH
Note 1 When a value other than ACH is written to the WDTE register, an internal reset signal is generated.
2. When performing bit operation instructions on the WDTE registers, an internal reset signal is generated.
3. The read value of the WDTE register is 9AH/1AH (different from the write value (ACH)).