CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4)
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5.8.5 Operation as input signal high and low level width measurement
Notice: When used as a LIN-bus support function, bit1 (ISC1) of the input switch control register (ISC) must be set to 1,
and in the following instructions, RxD0 must be used Instead of TImn.
TImn's signal width (high and low level widths) can be measured by starting counting on one edge
input at the TImn pin and capturing the count value on the other edge. The signal width of TImn can be
calculated using the following calculation formula.
Notice: Because the TImn pin input is sampled by the operating clock selected by the CKSmn bit of the timer mode
register mn (TMRmn), an error of 1 run clock is generated.
In Capture & Single Count mode, the timer count register mn (TCRmn) is used as an incremental
counter. If the channel start trigger bit (TSmn) of the timer channel start register m (TSm) is set to 1, the
TEmn bit becomes 1, and enters the start edge of the TImn pin to detect the wait state.
If the start edge of the TImn pin input (the rising edge of the TImn pin input when measuring the high
width) is detected, the count is incremented from 0000H onwards. Then, if a valid capture edge (the
falling edge of the TImn pin input when measuring the width of the high) is detected, the INTTMmn is
output at the same time as the count value is transferred to the timer data register mn (TDRmn). At this
point, if the counter overflows, the OVF position bit of the timer status register mn (TSRmn) is placed. If
the counter does not overflow, the OVF bit is cleared. The value of the TCRmn register becomes +1 and
the value transferred to the TDRmn register stops counting and enters the start edge of the TImn pin to
detect a wait state. After that, continue with the same run.
While snapping the count value to the TDRmn register, update the OVF bit of the TSRmn register
based on whether an overflow occurred during the measurement, and confirm the overflow state of the
captured value.
Even if the counter performs a full count of 2 cycles or more, it is considered that an overflow occurs
and the OVF bit of the TSRmn register is 1. However, in the event of 2 or more overflows, the interval
value cannot be measured normally by the OVF bit.
The CISmn1 and CISmn0 bits of the TMRmn register can be used to set whether the high or low
width of the TImn pin is measured. This feature is intended to measure the input signal width of the TImn
pin. Therefore, you cannot set the TSmn position to 1 during the period when the TEmn bit is 1.
CISmn1, CISmn0=10B of TMRmn register: Measure the width of the low level.
CISmn1, CISmn0=11B of TMRmn register: Measure the width of the high level.
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