CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4)
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5.2.3 Timer count register mn (TCRmn)
The TCRmn register is a 16-bit read-only register that counts the clock. Increments or decrements the
count in sync with the rising edge of the counting clock.
The operation mode is selected by the MDmn3 to MDmn0 bits of the Timer Mode Register mn
(TMRmn) to switch between incremental and decremental counting (refer to 5.3.3 Timer Mode Register mn
(TMRmn)).
Figure 5-3 Table of timer count register mn (TCRmn)
m: unit number (m=0,1) n: channel number (n=0~ 3).
The count value can be read by reading the timer count register mn (TCRmn).
In the following cases, the count value becomes FFFFH.
When a reset signal is generated.
When clearing the TM4mEN bit of the peripheral enable register 0 (PER0).
End of count of slave channels in PWM output mode.
At the end of the count of dependent channels in latency count mode.
At the end of the count of master/slave channels in single-trigger pulse output mode.
End of count of slave channels in multiple PWM output mode.
In the following cases, the count value becomes 0000H.
Enter Start when triggering in snap mode
At the end of the capture in snap mode
Note that even if the TCRmn register is read0, the count value is not captured to the timer data register mn (TDRmn).
As shown below, the read values of the TCRmn register vary depending on the operating mode and
operating state.
Table 5-2 Read values of the timer count register mn (TCRmn) in each operating mode
Note Indicates the read value of the TCRmn register when channel n is in the timer run stop state (TEmn=0) and the
count enable state (TSmn=1). Keep this value in the TCRmn register until the count begins.
Note m: unit number (m=0,1) n: channel number (n=0~3).
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