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Cmsemicon CMS32L051 - Port Output Mode Register (Pomxx)

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V1.2.2
CMS32L051 User Manual |Chapter 2 Pin Function
www.mcu.com.cn 27 / 703
2.3.7 Port output mode register (POMxx)
This is the register that sets the output mode in bits. When communicating serially with external devices
with different potentials and simple
I2C
communication with external devices with different potentials, an N-
channel open-drain output mode can be selected for the SDA xx pin.
After the reset signal is generated, the values of these registers become 00H.
Register address = base address + offset address; the base address of the POM register is 0x40040000,
and the offset address is shown in the figure below.
Note: For the bit set to N-channel open-drain output mode (POMmn=1), no internal pull-up resistor is connected.
Figure 2-7 Format of port output mode register
symbol
7
6
5
4
3
2
1
0
address
after reset
R/W
POM0
0
0
0
0
0
0
POM01
POM00
0x050
00H
R/W
POM1
POM17
POM16
POM15
POM14
POM13
POM12
POM11
POM10
0x051
00 H
R/W
POM2
POM27
POM26
POM25
POM24
POM23
POM22
POM21
POM20
0x052
00H
R/W
POM3
0
0
0
0
0
0
POM31
POM30
0x053
00H
R/W
POM4
0
0
0
0
0
0
POM41
POM40
0x054
00H
R/W
POM5
0
0
0
0
0
0
POM51
POM50
0x055
00H
R/W
POM6
0
0
0
0
POM63
POM62
POM61
Note 2
POM60
Note 2
0x056
00H
R/W
POM7
0
0
POM75
POM74
POM73
POM72
POM71
POM70
0x057
00H
R/W
POM12
0
0
0
0
0
0
0
POM120
0x05C
00H
R/W
POM13
POM137
POM136
0
0
0
0
0
POM130
0x05D
00H
R/W
POM14
POM147
POM146
0
0
0
0
0
POM140
0x05E
00H
R/W
POMmn
Selection of output mode for the Pmn pin (m=0~3, 5~7, 12~14, n=0~7).
0
Usual output mode
1
N-channel open-drain output mode
Note: 1 The initial value must be set for the unassigned bits.
2. It is limited to CMS32L051xx-S series products. For products other than the CMS32L051xx-S series, ports P60, P61
are dedicated N-channel open drain output ports and do not need to be configured with POM registers.
3. Ports P121~P124 do not have N-channel open-drain output function.

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