Cmsemicon CMS32L051 - Clock Operation Status Control Register (CSC)

V1.2.2
CMS32L051 User Manual |Chapter 4 Clock Generation Circuit
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4.3.3 Clock operation status control register (CSC)
This is a register that controls the operation of the high-speed system clock, the high-speed internal
oscillator clock, and the secondary system clock (except for the low-speed internal oscillator clock). Set the
CSC register via an 8-bit memory operation instruction.
After the reset signal is generated, the value of this register changes to C0H.
Figure 4-4 Format of clock operating status control register
Address: 40020401H After reset: C0H R/W
symbol
CSC
MSTOP
Operational control of the high-speed system clock
X1 oscillation mode
External clock input mode
Port mode
0
X1 oscillation circuit runs
The external clock of the
EXCLK pin is valid
Input/output ports
1
X1 oscillation circuit stops
The external clock on the
EXCLK pin is invalid
XTSTOP
Operational control of the subsystem clock
XT1 oscillation mode
External clock input mode
Port mode
0
XT1 oscillation circuit runs
The external clock of the
EXCLKS pin is valid
Input/output ports
1
XT1 oscillation circuit stops
The external clock of the
EXCLKS pin is invalid
HIOSTOP
Operation control of the high-speed internal oscillator clock
0
High-speed internal oscillator runs
1
High-speed internal oscillator stops
Note 1 After the reset is released, the CSC register must be set after the clock run-mode control register (CMC) is set.
2. After the reset is released and before the MSTOP position is 0, the oscillation settling time selection register
(OSTS) must be set. However, when using the OSTS register with the initial value, there is no need to set the
OSTS register.
3. To start the X1 oscillation by setting the MSTOP bit, the oscillation settling time of the X1 clock must be confirmed
through the state register (OSTC) of the oscillation settling time counter.
4. To start the XT1 oscillation by setting the XSTOP bit, you must wait through the software for the oscillation settling
time required by the subsystem clock.
5. The clock selected as the CPU/Peripheral Hardware Clock (fCLK) cannot be stopped through the CSC registers.
6. For the register flag setting and pre-stop conditions for stopping clock oscillation (external clock input is invalid),
refer to Table 4-2.
Table 4-2 Clock stop method
clock
Conditions before the clock stops (invalid external clock input)
Set the flag of the CSC
register
X1 clock
The CPU/peripheral hardware clock operates on a clock other than
the high-speed system clock.
(CLS=0 and MCS=0, or CLS=1).
MSTOP=1
External master system
clock
XT1 clock
The CPU/peripheral hardware clock operates on a clock other than
the secondary system clock.
(CLS=0)
XTSTOP=1
External subsystem
clock
High-speed internal
oscillator clock
The CPU/peripheral hardware clock runs on a clock other than the
high-speed internal oscillator clock.
(CLS=0 and MCS=1, or CLS=1).
HIOSTOP=1
7
6
5 4 3 2 1
0
MSTOn
XTSTOn
0
0
0
0
0
HIOSTOn