CMS32L051 User Manual | FLASH Control
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27.4.2 Chip erase
Chip erase, and the erase time are implemented by hardware and can also be configured via
FLCERCNT. The operation process is as follows:
1) Set FLERMD. ERMD0 is 1'b 1, select chip erase mode;
2) Set FLPROT to 0xF1 to unprotect FLOPMD. Then set FLOPMD1 to 0x55 and FLOPMD2 to 0xAA
3) Write arbitrary data to any address in the code flash area.
4) Software query status register FLSTS. OVF, OVF=1, indicates that the erase operation is complete.
5) Before proceeding with the next operation, the software sets 1 to clear the FLSTS.
27.4.3 Programming (word program).
WORD programming, write time is implemented by hardware or can be configured via PROCNT. The
operation process is as follows:
1) Set FLPROT to 0xF1 to unprotect FLOPMD. Then set FLOPMD1 to 0x AA and FLOPMD2 to 0x55
2) Writes the appropriate data to the destination address.
3) Software query status register FLSTS. OVF, OVF=1, indicates that the write operation is complete.
4) Before proceeding with the next operation, the software sets 1 to clear the FLSTS.
27.5 Flash read
The fastest finger frequency supported by the built-in FLASH of this device is 32 MHz. When the HCLK
frequency exceeds 32MHz, the hardware inserts a 1 wait period when the CPU accesses the FLASH.
27.6 Cautions for FLASH operation
⚫ FLASH memory has strict time requirements for the control signal of erasing and programming
operation, and the timing of the control signal is not qualified will cause the erase operation and programming
operation to fail. The setting of erasing and writing parameters can be implemented by hardware, or it can be
modified by software by modifying parameter registers; When using internal high-speed OCO,
MAINOSC/external input clock = 20M, it is recommended to use the hardware-set erasing parameters without
setting parameter registers.
⚫ If the erase and write operation is performed from within FLASH, the C PU stops taking the finger and
the hardware automatically waits for the operation to complete before proceeding to the next command. If the
operation is performed from the RAM, the CPU does not stop pointing and can now proceed to the next
command.
⚫ When FLASH is in programmatic operation, if the CPU executes the command to go to deep sleep,
the system will wait for the programming action to end before entering deep sleep.
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