CMS32L051 User Manual |Chapter 4 Clock Generation Circuit
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4.6.3 Example of setting up an XT1 oscillation circuit
After the reset is released, the CPU/peripheral hardware clock (f
CLK
) must be running at a high-speed
internal oscillator clock. Thereafter, if the XT1 oscillation clock is changed, the mode control register (OSMC),
the clock operation mode control register (CMC), and the clock run status control register (CSC) are provided
through the subsystem clock Set up the oscillation circuit and control the oscillation start, and set the XT1
oscillation clock to f
CLK
via the system clock control register (CKC).
[Register Setting] The registers must be set in order from (1) to (5).
(1) In deep sleep mode or sleep mode where the CPU is running at the subsystem clock, the RTCLPC
position 1 must be applied when only the real-time clock and the 15-bit interval timer are run at the
subsystem clock (ultra-low current consumption).
7 6 5 4 3 2 1 0
OSMC
(2) Put the OSCSELS position of the CMC register 1 so that the XT1 oscillation circuit runs.
7 6 5 4 3 2 1 0
CMC
AMPHS0 and AMPHS 1 bit: Set the oscillation mode of the XT1 oscillation circuit.
(3) Clear the XTSTOP bit of the CSC register to 0 so that the XT1 oscillation circuit begins to oscillate.
7 6 5 4 3 2 1 0
CSC
(4) The oscillation stabilization time required by the subsystem clock must be waited for through software
and timer functions, etc.
(5) Set the XT1 oscillation clock to the CPU/peripheral hardware clock through the CSS bit of the CKC
register.
7 6 5 4 3 2 1 0
CKC
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