Cmsemicon CMS32L051 - 12.5 3-wire serial I;O (SSPI00, SSPI01, SSPI10, SSPI11, SSPI20, SSPI21) communication

V1.2.2
CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit
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12.5 3-wire serial I/O (SSPI00, SSPI01, SSPI10, SSPI11, SSPI20, SSPI21)
communication
This is a clock synchronization communication function implemented by a total of 3 wires of serial clock
(SCLK) and serial data (SDI and SDO).
[Transmit and receive data]
 7-bit or 8-bit data length
 Phase control of sending and receiving data
• MSB/LSB preferred choice
[Clock control]
 Master or slave selection
 Phase control of input/output clocks
 Sets the transfer period generated by the prescaler and the in-channel counter.
 Maximum transfer rate
Note
Master communication: Max.f
CLK
/2 (SSPI00 only).
Master communication: Max.f
CLK
/4
Slave communication: Max.f
MCK
/6
[Interrupt function]
 End of transfer interrupt, buffer empty interrupt
[Error detection flag]
 Overflow error
Note It must be used within the scope of the SCLK Cycle Time (t
KCY
) characteristics. Please refer to the data sheet for
details.
Channels 0 to 3 of SCI0 and channels 0 to 1 of SCI1 support 3-wire serial I/O SSPI00, SSPI01, SSPI10,
SSPI11, SSPI20, SSPI21) channels.
3-wire serial I/O (SSPI00, SSPI01, SSPI10, SSPI11, SSPI20, SSPI21) has the following 6 types of
communication operation:
 Master transmission (see 12.5.1).
 Master reception (see 12.5.2).
 Master transmission and reception (refer to 12.5.3).
 Slave transmission (see 12.5.4).
 Slave reception (see 12.5.5).
 Slave transmission and reception (see 12.5.6).