CMS32L051 User Manual |Chapter 10 Watchdog Timer
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10.4.4 Setting watchdog timer interval interruption
Interval interrupt (INTWDTI) can be generated when 75% +1/2f
IL
of the overflow time is reached by setting
bit7 (WDTINT) of option byte (000C0H).
Table 10-5 Setting of watchdog timer interval interrupt
Note when the X1 oscillation clock is run after the deep sleep mode is released, the CPU starts running after the
oscillation stabilization time.
If the time from the release of the deep sleep mode to the overflow of the watchdog timer is short, the watchdog
overflow occurs within the oscillation stabilization time and a reset occurs. Therefore, if you want to run with the X1
oscillation clock and clear the watchdog timer after the interval interrupt is released from the deep sleep mode,
since the watchdog timer is not cleared after the oscillation settling time, this situation must be considered for the
setting of the overflow time.
Note Continue counting even after the INTWDTI is generated (continue until ACH is written to the Allowed Register
(WDTE) of the watchdog timer). If ACH is not written to the WDTE register before the overflow time, an internal
reset signal is generated.
10.4.5 Operation of the watchdog timer during LOCKUP
When the lockup_rst bit of the LOCKUP control register LOCKCTL is set to 1, once the core enters the
LOCKUP state, the low-speed internal oscillator begins to vibrate, the watchdog timer's timer automatically
starts running, and the control bit of the overflow time (WDCS2~WDCS0) is set to 3'b010, which means that
the overflow time is set to 12.8ms.
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