Cmsemicon CMS32L051 - Conditions before CPU Clock Transfer and Processing after Transfer

V1.2.2
CMS32L051 User Manual |Chapter 4 Clock Generation Circuit
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4.6.5 Conditions before CPU clock transfer and processing after transfer
The conditions before the CPU clock transfer and the handling after the transfer are as follows.
Table4-4 Regarding CPU clock transfer (1/2)
CPU clock
Conditions before transfer
Post-transfer processing
Before
transferring
After
transferring
High-speed
internal
oscillator clock
X1 clock
X1 oscillation is stable.
 OSCSEL=1, EXCLK=0, MSTOP=0
-oscillation settling time
If the oscillation of the high-speed
internal oscillator is stopped
(HIOSTOP=1), the operating current
can be reduced.
External master
system clock
Set the external clock of the EXCLK pin
input to active.
 OSCSEL=1, EXCLK=1, MSTOP=0
XT1 clock
XT1 oscillation is stable.
 OSCSELS=1, EXCLKS=0, XTSTOP=0
oscillation stabilization time
External
subsystem clock
Set the external clock of the EXCLKS pin
input to active.
 OSCSELS=1, EXCLKS=1, XTSTOP=0
X1 clock
High-speed
internal
oscillator clock
Allows high-speed internal oscillator
oscillation.
 HIOSTOP=0

Can stop the oscillation of X1
(MSTOP=1).
External master
system clock
Cannot be transferred.

XT1 clock
XT1 oscillation is stable.
 OSCSELS=1, EXCLKS=0, XTSTOP=0

Can stop the oscillation of X1
(MSTOP=1).
External
subsystem clock
Set the external clock of the EXCLKS pin
input to active.
 OSCSELS=1, EXCLKS=1, XTSTOP=0
Can stop the oscillation of X1
(MSTOP=1).
External master
system clock
High-speed
internal
oscillator clock
Allows high-speed internal oscillator
oscillation.
 HIOSTOP=0

Input to the external master system
clock can be set to be invalid
(MSTOP=1).
X1 clock
Cannot be transferred.

XT1 clock
XT1 oscillation is stable.
 OSCSELS=1, EXCLKS=0, XTSTOP=0

Input to the external master system
clock can be set to be invalid
(MSTOP=1).
External
subsystem clock
Set the external clock of the EXCLKS pin
input to active.
 OSCSELS=1, EXCLKS=1, XTSTOP=0
Input to the external master system
clock can be set to be invalid
(MSTOP=1).