Cmsemicon CMS32L051 - 1.4 SWD interface pin

V1.2.2
CMS32L051 User Manual |Chapter 1 CPU
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1.4 SWD interface pin
The two GPIOs of this product can be used as SWD interface pins, which are present in all packages.
Table 1-1 SWD debug port pins
When the SWD function is not used, SWD can be disabled by setting the debug stop control register
(DBGSTOPCR).
Bit No.
31
30
29
28
27
26
25
24
DBGSTOPCR
-
-
-
-
-
-
-
SWDIS
default value
0
0
0
0
0
0
0
0
Bit No.
23
22
21
20
19
18
17
16
DBGSTOPCR
-
-
-
-
-
-
-
-
default value
0
0
0
0
0
0
0
0
Bit No.
15
14
13
12
11
10
9
8
DBGSTOPCR
-
-
-
-
-
-
-
-
default value
0
0
0
0
0
0
0
0
Bit No.
7
6
5
4
3
2
1
0
DBGSTOPCR
-
-
-
-
-
-
FRZEN1
FRZEN0
default value
0
0
0
0
0
0
0
0
SWDIS
SWD debug interface status
0
The SWD debug interface is enabled. P40 cannot be used as a GPIO when the debugger is
connected (because the ENO and DOUT of the IOBUF are controlled by the debugger at this time)
1
The SWD debug interface is disabled. The P40 can be used as a GPIO
FRZEN0
In the state where the debugger is connected and the CPU is in the debug state (HALTED=1), the
timer is peripheral module action/stop
Note 1
0
Peripheral actions
1
Peripheral stops
FRZEN1
In the state where the debugger is connected and the CPU is in the debug state (HALTED=1), the
communication system peripheral module action/stop
Note 2
0
Peripheral actions
1
Peripheral stops
Note 1: The timer peripheral modules of this product include: Timer4, a universal timer unit.
Note 2: The peripheral modules of the communication system of this product include: communication serial
communication unit, serial IICA.
SWD port name
Debugging capabilities
Pin assignment
SWCLK
Serial clock
P137
SWDIO
Serial data input/output
P40