Cmsemicon CMS32L051 - Control Data Allocation

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CMS32L051 User Manual |Chapter 16 Enhanced DMA

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16.3.2 Control data allocation

Starting from the start address, follow DMACRj, DMBLSj, DMACTj, DMRLDj, DMSARj, DMDARj (

j=0~23) registers are assigned control data sequentially.

The start address is set by the DMABAR register, and the lower 10 bits are set separately by the

vector table assigned by each startup source.

The distribution of control data is shown in Figure 16-3.

Note 1 The DMAENi0~DMAENi7 bits must be 0 in the corresponding DMAENi (i=0~2). (Disable Startup) when changing

DMACRj, DMBLSj, DMACTj, DMRLDj, DMSARj, DMSARj, Data for the DMDARj register.

2. DMACRj, DMBLSj, DMACTj, DMRLDj, DMSARj and DMA cannot be transmitted via DMA Access to DMDARj.

Figure 16-3 Control data allocation (DMABAR set to 2000000H)

Main Page

default chapter2
- Documentation Instructions2
- Table of Contents3
Chapter 1 CPU14
- 1.1 Overview14
- 1.2 Cortex-M0+ Core Features14
- 1.3 Debugging Features14
- 1.4 SWD Interface Pin16
- 1.5 ARM Reference Document17
Chapter 2 Pin Function18
- 2.1 Port Function18
- 2.2 Port Multiplexing Function18
- 2.3 Registers for Controlling Port Functions19
- Port Mode Register (Pmxx)21
- Port Register (Pxx)22
- Port Set Control Register (Psetxx)23
- Port Clear Control Register (Pclrxx)24
- Pull-Up Resistor Selection Register (Puxx)25
- Pull-Down Resistor Selection Register (Pdxx)26
- Port Output Mode Register (Pomxx)27
- Port Mode Control Register (Pmcxx)28
- Port Output Multiplexing Function Configuration Register (Pxxcfg)29
- Port Input Multiplexing Function Configuration Registers33
- Ti13Pcfg, Intp0Pcfg, Intp1Pcfg , Intp2Pcfg, Intp3Pcfg, Sdi00Pcfg, Sclki00Pcfg, Ss00Pcfg , Sdi20Pcfg, Sclki20Pcfg, Sdaa0Pcfg, Scla0Pcfg, Rxd1Pcfg )33
- SPI Port Multiplexing Configuration Register (SPIPCFG)37
- 2.4 Handling of Unused Pins38
- Register Setting When Using the Multiplexed Function39
- Basic Idea When Using the Multiplexed Output Feature39
- Example of Register Settings Using Port Functions and Multiplexing Functions40
- EPWM Port Configuration Method56
Chapter 3 System Structure57
- 3.1 Overview57
- 3.2 System Address Partition58
Chapter 4 Clock Generation Circuit60
- 4.1 Function of the Clock Generation Circuit60
- 4.2 Structure of Clock Generation Circuit62
- 4.3 Registers for Controlling Clock Generation Circuit65
- Clock Operation Mode Control Register (CMC)65
- System Clock Control Register (CKC)67
- Clock Operation Status Control Register (CSC)68
- Status Register of the Oscillation Stabilization Time Counter (OSTC)69
- Oscillation Stabilization Time Selection Register (OSTS)71
- Peripheral Enable Registers 0, 1 (PER0, PER1)72
- Subsystem Clock Supply Mode Control Register (OSMC)76
- High-Speed Internal Oscillator Frequency Selection Register (HOCODIV)77
- High-Speed Internal Oscillator Trim Register (HIOTRM)78
- Subsystem Clock Selection Register (SUBCKSEL)79
- 4.4 System Clock Oscillation Circuit80
- X1 Oscillation Circuit80
- XT1 Oscillation Circuit80
- High-Speed Internal Oscillator84
- Low-Speed Internal Oscillator84
- 4.5 Operation of Clock Generation Circuit85
- Clock Control87
- Example of Setting up a High-Speed Internal Oscillator87
- Example of Setting up an X1 Oscillation Circuit89
- Example of Setting up an XT1 Oscillation Circuit90
- State Transition Graph of the CPU Clock91
- Conditions before CPU Clock Transfer and Processing after Transfer97
- Time Required to Switch between CPU Clock and Main System Clock99
- Condition before the Clock Oscillation Stops100
- 4.7 High-Speed Internal Oscillation Correction101
- High-Speed Internal Oscillation Self-Adjustment Function101
- Register Description102
- Operation Description103
- Precautions for Use106
Chapter 5 Universal Timer Unit (Timer4)107
- 5.1 Function of Universal Timer Unit108
- Independent Channel Operation Function108
- Multi-Channel Linkage Operation Function110
- 8-Bit Timer Operation Function (Limited to Channel 1 and Channel 3 of Unit 0)111
- LIN-Bus Support Functions (Channel 3 of Unit 0 Only)111
- 5.2 Structure of the Universal Timer Unit112
- List of Universal Timer Unit 0 Registers115
- List of Universal Timer Unit 1 Registers116
- Timer Count Register Mn (Tcrmn)117
- Timer Data Register Mn (Tdrmn)118
- 5.3 Registers for Controlling General-Purpose Timer Unit119
- Peripheral Enable Register 0 (PER0)120
- Timer Clock Select Register M (Tpsm)121
- Timer Mode Register Mn (Tmrmn)124
- Timer Status Register Mn (Tsrmn)129
- Timer Channel Enable Status Register M (Tem)130
- Timer Channel Start Register M (Tsm)131
- Timer Channel Stop Register M (Ttm)132
- Timer Input-Output Select Register (TIOS0)133
- Timer Output Enable Register M (Toem)134
- Timer Output Register M (Tom)135
- Timer Output Level Register M (Tolm)136
- Timer Output Mode Register M (Tomm)137
- Noise Filter Enable Register 1 (NFEN1)138
- Noise Filter Enable Register 2 (NFEN2)139
- Registers for Controlling Timer Input/Output Pin Port Functions140
- 5.4 Basic Rules of the Universal Timer Unit141
- Basic Rules of the Multi-Channel Linkage Operation Function141
- Basic Rules for the 8-Bit Timer to Operate the Function143
- 5.5 Operation of the Counter144
- Count Clock (F TCLK )144
- Start Timing of Counter146
- Operation of Counter147
- Control of the Channel Output (Tomn Pin)152
- Structure of the Tomn Pin Output Circuit152
- Output Setting of the Tomn Pin153
- Cautions for Channel Output Operation154
- One-Time Operation of the Tomn Bit158
- Timer Interrupt and Tomn Pin Output When Counting Starts159
- Control of Timer Input (Timn)160
- Structure of Timn Pin Input Circuit160
- Noise Filter161
- Considerations When Manipulating Channel Inputs162
- 5.8 Independent Channel Operation Function of the Universal Timer Unit163
- Operates as an Interval Timer / Square Wave Output163
- Operate as External Event Counter167
- Operates as Frequency Divider170
- Operates as Input Pulse Interval Measurement173
- Operation as Input Signal High and Low Level Width Measurement176
- Operation as Delay Counter180
- 5.9 Multi-Channel Linkage Operation of the Universal Timer Unit183
- Operates as Single-Trigger Pulse Output Function183
- Operates as PWM Function190
- Operates as Multiplex PWM Output Function197
Chapter 6 Function of EPWM Output Control Circuit205
- 6.1 Structure of the Output Control Circuit205
- 6.2 Registers for Controlling EPWM Output Control Circuit206
- Peripheral Enable Register 1 (PER1)207
- EPWM Input Source Selection Register (EPWMSRC)207
- EPWM Output Control Register (EPWMCTL)207
- EPWM Force Truncated Input Selection Register (EPWMSTC)208
- EPWM Force Truncated Output Selection Register (EPWMSTL)209
- EPWM Status Register (EPWMSTR)209
- 6.3 Operation of EPWM Output Control Circuit211
- Initial Setup211
- Normal Operation212
- Force Truncation Processing212
- 6.4 Control Example of Brushless DC Motor214
- Example of a Hardware Connection214
- Control Timing of Three-Phase Brushless DC Motors215
- Example of Register Setting216
- 6.5 Example of Stepper Motor Control217
- Example of a Hardware Connection217
- Control Method218
- Example of Register Setting219
Chapter 7 Real-Time Clock220
- 7.1 Function of Real-Time Clock220
- 7.2 Structure of Real-Time Clock220
- 7.3 Registers for Controlling Real-Time Clock222
- Peripheral Enable Register 0 (PER0)223
- Real-Time Clock Selection Register (RTCCL)224
- Real-Time Clock Control Register0 (RTCC0)225
- Real-Time Clock Control Register1 (RTCC1)226
- Clock Error Correction Register (SUBCUD)228
- Second Count Register (SEC)229
- Minute Count Register (MIN)229
- Hour Count Register (HOUR)230
- Day Count Register (DAY)232
- Week Count Register (WEEK)233
- Month Count Register (MONTH)234
- Year Count Register (YEAR)234
- Alarm Minute Register (ALARMWM)235
- Alarm Hour Register (ALARMWH)235
- Alarm Week Register (ALARMWW)236
- Port Mode Register and Port Register236
- Operation of Real-Time Clock237
- Start of Real-Time Clock Operation237
- Shifting to Sleep Mode after Starting Operation238
- Read and Write to the Real-Time Clock Counter239
- Alarm Setting for Real-Time Clock241
- 1Hz Output of the Real-Time Clock242
- Example of Clock Error Correction for a Real-Time Clock243
Chapter 8 15-Bit Interval Timer245
- 8.1 Function of 15-Bit Interval Timer245
- 8.2 Structure of 15-Bit Interval Timer245
- 8.3 Registers for Controlling 15-Bit Interval Timer246
- Peripheral Enable Register 0 (PER0)246
- Real-Time Clock Selection Register (RTCCL)247
- 15-Bit Interval Timer Control Register (ITMC)248
- 8.4 15-Bit Interval Timer Operation249
- 15-Bit Interval Timer Operation Timing249
- Start of Count Operation and Re-Enter to Sleep Mode after Returned from Sleep Mode250
Chapter 9 Clock Output/Buzzer Output Controller251
- 9.1 Functions of Clock Output/Buzzer Output Controller251
- 9.2 Structure of Clock Output/Buzzer Output Controller253
- 9.3 Registers for Controlling Clock Output/Buzzer Output Controller253
- Clock Output Select Register N (Cksn)253
- 9.4 Operation of Clock Output/Buzzer Controller256
- Operation of Output Pin256
- 9.5 Cautions for Clock Output/Buzzer Output Control Circuitry256
Chapter 10 Watchdog Timer257
- Function of Watchdog Timer257
- Structure of Watchdog Timer257
- Registers for Controlling Watchdog Timer259
- Watchdog Timer Enable Register (WDTE)259
- LOCKUP Control Register (Lockctl)And Its Protection Register (PRCR)260
- Operation of the Watchdog Timer261
- Operational Control of the Watchdog Timer261
- Watchdog Timer Overflow Time Setting262
- Setting Window Open Period of Watchdog Timer263
- Setting Watchdog Timer Interval Interruption264
- Operation of the Watchdog Timer During LOCKUP264
- A/D Converter265
- Function of A/D Converter265
- Control Registers of A/D Converter267
- Peripheral Enable Register 0 (PER0)268
- A/D Converter Mode Register 0 (ADM0)269
- A/D Converter Mode Register 1 (ADM1)274
- A/D Converter Mode Register 2 (ADM2)275
- A/D Converter Trigger Mode Register (ADTRG)276
- Analog Input Channel Specification Register (ADS)277
- 12-Bit A/D Conversion Result Register (ADCR)279
- 8-Bit A/D Conversion Result Register (ADCRI)280
- Conversion Result Comparison Upper Limit Setting Register (ADUL)280
- Conversion Result Comparison Lower Limit Setting Register (ADLL)280
- A/D Converter Sampling Time Extension Control Register (ADSMPWAIT)281
- Registers for Controlling the Function of the Analog Input Pin Port281
- Input Voltage and Conversion Results282
- Operation Mode of A/D Converter283
- Software Trigger Mode (Select Mode, Continuous Conversion Mode)283
- Software Trigger Mode (Select Mode, Single Conversion Mode)284
- Software Trigger Mode (Scan Mode, Continuous Conversion Mode)285
- Software Trigger Mode (Scan Mode, Single Conversion Mode)286
- Hardware Triggered No-Wait Mode (Select Mode, Continuous Conversion Mode)287
- Hardware Trigger No-Wait Mode (Select Mode, Single Conversion Mode)288
- Hardware Trigger No-Wait Mode (Scan Mode, Continuous Conversion Mode)289
- Hardware Trigger No-Wait Mode (Scan Mode, Single Conversion Mode)290
- Hardware Trigger Wait Mode (Select Mode, Continuous Conversion Mode)291
- Hardware Trigger Wait Mode (Select Mode, Single Conversion Mode)292
- Hardware Trigger Wait Mode (Scan Mode, Continuous Conversion Mode)293
- Hardware Trigger Wait Mode (Scan Mode, Single Conversion Mode)294
Chapter 12 Universal Serial Communication Unit295
- Function of Universal Serial Communication Unit296
- 3-Wire Serial I/O (SSPI00, SSPI01, SSPI10, SSPI11, SSPI20, SSPI21)296
- Uart (Uart0~Uart2)297
- Simple I 2 C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21)298
- Structure of Universal Serial Communication Unit299
- Shift Register302
- Registers for Controlling Universal Serial Communication Unit304
- Peripheral Enable Register 0 (PER0)305
- Serial Clock Select Register M (Spsm)306
- Serial Mode Register Mn (Smrmn)307
- Serial Communication Operation Setting Register Mn (Scrmn)309
- Serial Data Register Mn (Sdrmn)311
- Serial Flag Clear Trigger Register Mn (Sirmn)313
- Serial Status Register Mn (Ssrmn)314
- Serial Channel Start Register M (Ssm)316
- Serial Channel Stop Register M (Stm)317
- Serial Channel Enable Status Register M (Sem)318
- Serial Output Enable Register M(Soem)319
- Serial Output Register M (Som)320
- Serial Output Level Register M (Solm)321
- Input Switching Control Register (ISC)323
- Noise Filter Enable Register 0 (NFEN0)324
- Registers Controlling the Function of the Serial Input/Output Pin Port325
- Operation Stop Mode326
- Stopping the Operation by Units326
- Stopping the Operation by Channels327
- 3-Wire Serial I/O (SSPI00, SSPI01, SSPI10, SSPI11, SSPI20, SSPI21) Communication328
- Master Transmission329
- Master Reception338
- Master Transmission and Reception346
- Slave Transmission354
- Slave Receiving362
- Slave Send and Receive368
- Calculation of Transmit Clock Frequency377
- Procedure for Handling Errors During 3-Wire Serial I/O Communication (SSPI00, SSPI01, SSPI10, SSPI11, SSPI20, SSPI21)379
- Operation of Clock-Synchronous Serial Communication with Slave Selection Input Function380
- Slave Transmission383
- Slave Receiving393
- Slave Transmission and Reception400
- Calculation of the Transmit Clock Frequency410
- Procedure for Handling Errors During Clock-Synchronous Serial Communication with the Slave Selection Input Function411
- Operation of UART (UART0~UART2) Communication412
- UART Transmission413
- UART Reception422
- Calculation of the Baud Rate429
- Handling Steps When an Error Occurs During UART (UART0~UART 2) Communication433
- Operation of LIN Communication434
- LIN Transmission434
- LIN Reception437
- Simplified I C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21) Communication Operation442
- Address Segment Transmission443
- Data Transmission448
- Data Reception451
- Generation of Stop Condition455
- Calculation of the Transfer Rate456
- Processing Steps When an Error Occurs in a Simple I2C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21)458
- Communication Process458
Chapter 13 Serial Interface SPI459
- Serial Interface SPI Function459
- Structure of SPI459
- Registers for Controlling SPI460
- Peripheral Enable Register 0 (PER0)461
- SPI Operating Mode Register (SPIM)462
- SPI Clock Selection Register (SPIC)463
- Transmit Buffer Registers (SDRO)464
- Receive Buffer Register (SDRI)464
- SPI Pin Port Function Control Register465
- Operation of SPI466
- Master Tramission and Reception467
- Master Reception470
- Slave Send and Receive473
- Slave Reception476
Chapter 14 Serial Interface IICA479
- Function of IICA479
- Structure of the Serial Interface IICA482
- Registers for Controlling Serial Interface IICA485
- Peripheral Enable Register 0 (PER0)486
- IICA Control Register N0 (Iicctln0)486
- IICA Status Register N (Iicsn)491
- IICA Flag Register N (Iicfn)493
- IICA Control Register N1 (Iicctln1)495
- IICA Low Level Width Setting Register N (Iicwln)497
- IICA High Level Width Setting Register N (Iicwhn)497
- Registers Controlling the IICA Pin Port Function498
- Function of I C-Bus Mode499
- Pin Structure499
- Setting the Transmit Clock Via Iicwln Register and Iicwhn Register500
- Definition and Control Method of I C-Bus501
- Start Conditions502
- Address503
- Designation of Transmission Direction503
- Acknowledge (ACK)504
- Stop Conditions505
- Wait506
- Release Method of Wait508
- Interrupt Request (Intiican) Generation Timing and Wait Control509
- Detection Method for Address Matching510
- Detection of Errors510
- Extension Code511
- Arbitration512
- Wake-Up Function514
- Communicate with Reservation517
- Other Cautions521
- Communication Operation522
- Generation Timing of I C Interrupt Request (Intiican)531
- Timing Diagram552
Chapter 15 Irda568
- Function of Irda568
- Registers for Controlling the Irda569
- Peripheral Enable Register 0 (PER0)569
- Irda Control Register (IRCR)570
- Operation of Irda571
- Operating Steps for Irda Communication571
- Transmission572
- Reception572
- High Level Pulse Width Selection573
- Considerations When Using Irda573
Chapter 16 Enhanced DMA574
- The Function of DMA574
- Structure of DMA576
- Registers for Controlling DMA577
- DMA Control Data Areas and DMA Vector Table Areas Allocation578
- Control Data Allocation579
- Vector Table581
- Peripheral Enable Register 1 (PER1)583
- DMA Control Register J(Dmacrj) (J=0~23)583
- DMA Block Size Register J (Dmblsj) (J=0~23)585
- DMA Transmit Count Register J(Dmactj) (J=0~23)586
- DMA Transmit Count Reload Register J(Dmrldj) (J=0~23)587
- DMA Source Address Register J(Dmsarj) (J=0~23)588
- DMA Destination Address Register J(Dmdarj) (J=0~23)588
- DMA Boot Enable Register I (Dmaeni) (I=0~2)589
- DMA Base Address Register (DMABAR)591
- DMA Operation592
- Start the Source592
- Normal Mode593
- Repeat Pattern596
- Chain Transfer599
- Precautions When Using DMA601
- DMA Controls the Settings of Data and Vector Tables601
- DMA Controls the Allocation of Data Areas and DMA Vector Table Areas601
- Number of Execution Clocks for DMA602
- Response Time of DMA603
- Startup Source for DMA603
- Operation in Standby Mode604
Chapter 17 Linkage Controller (EVENTC)605
- Feature of EVENTC605
- Structure of EVENTC605
- Control Registers606
- Output Target Selection Register N (Elselrn) (N=00~14)607
- Operation of EVENTC610
Chapter 18 Interrupt Function611
- Types of Interrupt Function611
- Interrupt Source and Structure611
- Registers Controlling Interrupt Function616
- Interrupt Request Flag Registers (IF00 to IF31)616
- Interrupt Mask Flag Register (MK00~MK31)617
- Register (EGN0)618
- Operation of Interrupt Handling622
- Acceptance of Maskable Interrupt Requests622
- Acceptance of Non-Maskable Interrupt Requests622
Chapter 19 Key Interrupt Function623
- Function of Key Interrupt623
- Structure of Key Interrupt623
- Registers for Controlling Key Interrupt625
- Key Return Mode Register (KRM)625
- Port Mode Register (Pmx)626
Chapter 20 Standby Function627
- Standby Function627
- Sleep Mode628
- Setting of the Sleep Mode628
- Release of Sleep Mode631
- Deep Sleep Mode632
- The Setting for Deep Sleep Mode632
- Release of Deep Sleep Mode634
Chapter 21 Reset Function636
- Register for Confirming the Reset Source641
- Reset Control Flag Register (RESF)641
Chapter 22 Power-On Reset Circuit644
- Function of Power-On Reset Circuit644
- Structure of Power-On Reset Circuit645
- Operation of Power-On Reset Circuit645
Chapter 23 Voltage Detection Circuit649
- Function of Voltage Detection Circuit649
- Structure of Voltage Detection Circuit650
- Registers for Controlling Voltage Detection Circuit651
- Voltage Sense Register (LVIM)651
- Voltage Sense Level Register (LVIS)652
- Operation of Voltage Detection Circuit655
- Settings When Used in Reset Mode655
- Settings When Used in Interrupt Mode657
- Settings for Interrupt & Reset Mode659
- Considerations for Voltage Detection Circuits665
Chapter 24 Security Features667
- Overview667
- Registers Used by Security Functions668
- Operation of Security Functions668
- Flash CRC Operation Function (High-Speed CRC)668
- CRC Operation Function (General CRC)672
- RAM Parity Error Detection Function675
- SFR Protection Function677
- Frequency Detection Function678
- A/D Test Function679
- Digital Output Signal Level Detection Function for Input/Output Pin681
- Product Unique Identification Register682
Chapter 25 Temperature Sensor683
- Function of Temperature Sensor683
- Register for Temperature Sensor683
- Temperature Sensor Calibration Data Register TSN25683
- Temperature Sensor Calibration Data Register TSN85683
- Instructions for Use with the Temperature Sensor684
- How the Temperature Sensor Is Used684
- How to Use the Temperature Sensor685
Chapter 26 Option Byte686
- Function of Option Byte686
- User Option Bytes (000C0H~000C2H)686
- Flash Data Protection Option Bytes (000C3H, 500004H)687
- Format of User Option Byte688
- Format of Flash Data Protection Option Bytes694
Chapter 27 FLASH Control695
- Description of FLASH Control695
- Structure of FLASH Memory695
- Registers for Controlling FLASH696
- Flash Write Protection Register (FLPROT)696
- FLASH Operation Control Registers (FLOPMD1, FLOPMD2)697
- Flash Erase Control Register (FLERMD)697
- Flash Status Register (FLSTS)698
- Flash Full-Chip Erase Time Control Register (FLCERCNT)698
- Flash Sector Erase Time Control Register (FLSERCNT)699
- Flash Write Time Control Register (FLPROCNT)700
- FLASH Operation Method701
- Sector Erase701
- Chip Erase702
- Programming (Word Program)702
- Flash Read702
- Cautions for FLASH Operation702
Appendix Revision History703

Cmsemicon CMS32L051 - Control Data Allocation

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