Cmsemicon CMS32L051 - Hardware Trigger No-Wait Mode (Select Mode, Single Conversion Mode)

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CMS32L051 User Manual |Chapter 11 A/D Converter
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11.4.6 Hardware trigger no-wait mode (select mode, single conversion mode)
(1) In the stop state, the ADCE bit of the mode register 0 (ADM0) of the A/D converter is 1 and enters
the A/D transition standby state.
(2) After counting the steady wait time (1 us) by software, the ADCS bit of the ADM0 register is 1 into a
hardware-triggered standby state (this phase does not begin the transition). When the hardware
triggers standby, the A/D transition does not start even when the ADCS bit 1 is applied.
(3) If the input hardware triggers in the state where the ADCS bit is 1, the analog input specified by the
analog input channel specified register (ADS) is A/D converted.
(4) If the A/D conversion ends, the conversion results are saved to the A/D conversion result register
(ADCR, ADCRH) and an A/D conversion end interrupt request signal (INTAD) is generated).
(5) After the A/D conversion ends, the ADCS bit remains in the state of 1 and enters the A/D transition
standby state.
(6) If the input hardware triggers during the conversion, the current A/D conversion is aborted
immediately and then restarted.
(7) If the ADS registers are overwritten or overwritten during the conversion, the current A/D conversion
is aborted immediately, and then the analog input respecified by the ADS register is A/D converted.
(8) If you override the 1 to the ADCS bit during the conversion, the current A/D conversion is aborted
immediately and the conversion begins again.
(9) If the ADCS bit is 0 during the conversion process, the current A/D conversion stops immediately
and then enters the A/D transition standby state. However, in this state, the A/D converter does not
enter the stopped state.
(10) If the ADCE bit is 0 in the A/D transition standby state, the A/D converter enters a stopped state.
When the ADCS bit is 0, even the input hardware trigger is ignored and the A/D conversion does
not begin.
Figure11-21 Timing example of hardware trigger no-wait mode (select mode, sequential conversion mode)
set 1 to ADCE bit
generate hardware trigger
generate hardware
trigger during A/D
conversion operation
clear ADCE bit to 0
rewrite ADCS bit to 1 during A/D
conversion operation
clear ADCS bit to 0 during
conversion
do not accept trigger
auto restart
conversion when
conversion completes

auto restart
conversion when
conversion completes

auto restart
conversion when
conversion completes

 conversion completes
A/D conversion state
stop
converting
idle conversion idle conversion
idle
conversion
idle
conversion
idle
conversion
(ANI1)
idle
conversion
stop
converting
modify ADS (from ANI0 to
ANI1) during A/D conversion
set 1 to ADCS bit
do not accept trigger trigger idle
hardware trigger