Cmsemicon CMS32L051 - Real-Time Clock Control Register1 (RTCC1)

V1.2.2
CMS32L051 User Manual |Chapter 7 Real-Time Clock
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7.3.4 Real-time clock control register1 (RTCC1)
This is the 8-bit register that controls the alarm interrupt function and the counter waits. The RTCC1
register is set via an 8-bit memory operation command. After the reset signal is generated, the value of
this register becomes 00H.
Figure 7-5 Format of real-time clock control register 1 (RTCC1) (1/2)
Address: 0x40044F5E After reset: 00H R/W
symbol
RTCC1
WHALES
Alarm clock operation control
0
Consistent operation is invalid.
1
Consistent operation is valid.
To set the WALE bit while the counter is running (RTCE=1) and the NULLE bit is 1, it must be overridden
after setting the INTRTC to disable interrupt handling through the interrupt mask flag register. And the
WAFG flag and the RTCIF flag must be cleared after rewriting. To set each alarm register (AL flag for
RTCC1 register, alarm clock minute register (ALARMWM), alarm hour register (ALARMWH) and alarm
clock day registers (ALARMWW)), the WALE set to 0 (consistent operation is invalid).
WALIE
Operation control of alarm interrupt (INTRTC) function
0
No alarm clock consistent interruptions are generated.
1
Generates an alarm clock consistent interrupt.
WAFG
Alarm detection status flag
0
Alarm clock is inconsistent.
1
Alarm clock consistency detected.
This is a status flag that indicates that the alarm clock is detected consistently. Valid only when the WALE
bit is 1 and becomes 1 when the alarm clock is detected to be consistent and 1 f
RTC
clock has passed.
Clear this flag by writing 0 to this flag. The action to write 1 is invalid.
7
6
5
4
3
2
1
0
INBut
WALIE
0
WAFG
RIFG
0
RWST
RWHas