CMS32L051 User Manual |Chapter 7 Real-Time Clock
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Figure 7-5 Format of real-time clock control register 1 (RTCC1) (2/2)
Fixed-period interrupt status flag
No fixed-cycle interruptions are generated.
A fixed-cycle interruption is generated.
This is a status flag that indicates a fixed-cycle interruption. This flag is 1 when a fixed-period interrupt
occurs. Clear this flag by writing 0 to this flag. The action to write 1 is invalid.
Wait status flag for the real-time clock
It is in the counter read/write mode.
This is the state that indicates whether the setting of the RWAIT bit is valid or not. The read and write
count value must be read and written after confirming that this flag is 1.
Wait control of the real-time clock
Set the SEC~YEAR counter to stop running and enter the read and write mode of the counter.
This bit controls the operation of the counter. To read and write the count value, you must write 1 to this
bit.
Because the internal counter (16-bit) continues to run, the read and write must end within 1 second and
then return to 0.
It takes up to 1 f
RTC
clock from placing the RWAIT set to 1 to being able to read and write the count value
(RWSt=1).
If an internal counter (16-bit) overflow occurs when the RWAIT bit is 1, the overflow is maintained and the
count is incremented after the RWAIT bit becomes 0.
However, when the seconds count register is written, the overflow is not kept in the state.
Remark 1. Fixed-cycle interrupts and alarm clock consistent interrupts use the same interrupt source (INTRTC). In the
case of using these two interrupts at the same time, INTRTC can occur to determine which interrupt occurred by
acknowledging the fixed-period interrupt status flag (RIFG) and the alarm detection status flag (WAFG).
2. If the seconds count register (SEC) is written, the internal counter (16-bit) is cleared.
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