CMS32L051 User Manual |Chapter 4 Clock Generation Circuit
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4.3.4 Status register of the oscillation stabilization time counter (OSTC)
This is the register that indicates the counting status of the oscillation settling time counter of the X1 clock.
It is possible to confirm the oscillation settling time of the X1 clock in the following cases.
When the CPU clock is a high-speed internal oscillator clock or a subsystem clock and the oscillation
of the X1 clock begins
The OST register can be read via 8-bit memory operation instructions when the CPU clock is a high-
speed internal oscillator clock and the sleep mode is released after moving to deep sleep mode in the state of
X1 clock oscillation.
The value of this register becomes 00H by resetting the signal generation, entering deep sleep mode, or
the MSTOP bit (bit7 of the clock operating state control register (CSC)) is 1.
Note The oscillation settling time counter starts counting in the following cases:
When the X1 clock starts oscillating (EXCLK, OSCSEL=0, 1 MSTOP=0).
released
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