CMS32L051 User Manual |Chapter 4 Clock Generation Circuit
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Figure 4-5 Format of status register of the oscillation stabilization time counter (OSTC)
Address: 40020402H After reset: 00H R
Symbol
7 6 5 4 3 2 1 0
OSTC
Note 1 After the above time, you start with MOST8 bits and change to 1 and remain in the state of 1.
2. The oscillation stabilization time counter only counts during the oscillation stabilization time set by the
oscillation stabilization time selection register (OSTS). In the following cases, the oscillation settling time of the
OSTS register must be set to be greater than the count value confirmed by the OSTC register.
-speed internal oscillator clock or a subsystem clock and oscillation of the X1
clock is to begin
When the CPU clock is a high-speed internal oscillator clock and is released from deep sleep mode after being
shifted to deep sleep mode with the X1 clock oscillating (so it must be noted that the OSTC register after being
released from deep sleep mode only sets the state for the oscillation settling time set in the OSTS register).
3. The oscillation stabilization time of the X1 clock does not include the time before the clock starts oscillating (See
Figure a as below).
Deep sleep mode is released
X1 pin
Voltage waveform
a
Note f
X
: X1 clock oscillation frequency
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