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CMS32L051 User Manual |Chapter 16 Enhanced DMA
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Table 16-5 DMA startup source and vector address
DMA start source (the source where the interrupt
request occurred).
The source
number
The address of the vector
Priority
Flash read-write erase ends
0
The setting address of the DMABAR
register is +00H
high
low
INTP0
1
The setting address of the DMABAR
register is +01H
INTP1
2
The setting address of the DMABAR
register is +02H
INTP2
3
The setting address of the DMABAR
register is +03H
INTP3
4
The setting address of the DMABAR
register is +04H
The A/D conversion ends
5
The setting address of the DMABAR
register is +05H
retain
6
The setting address of the DMABAR
register is +06H
retain
7
The setting address of the DMABAR
register is +07H
The end of transmission received by UART0 /
the end of transmission of SSPI01 or the end of
transmission of buffer NULL/IIC01
8
The setting address of the DMABAR
register is +08H
The end of the UART0 transmission / the end of
the SSPI00 transmission or the end of the buffer
NULL/IIC00 transmission
9
The setting address of the DMABAR
register is +09H
The end of transmission received by UART1 /
the end of transmission of SSPI11 or the end of
transmission of buffer NULL/IIC11
10
The setting address of the DMABAR
register is +0AH
End of transmission for UART1 transmission/end
of transmission for SSPI10 or end of
transmission for buffer NULL/IIC10/end of
transmission for SPI
11
The setting address of the DMABAR
register is +0BL
The end of transmission received by UART2 /
the end of transmission of SSPI21 or the end of
transmission of buffer NULL/IIC21
12
The setting address of the DMABAR
register is +0CH
The end of the UART2 transmission / the end
of the SSPI20 transmission or the end of the
buffer null/IIC20 transmission
13
The DMABAR register is set to address
+0DH
IICA0 communication ends.
14
The setting address of the DMABAR
register is +0EI
A 15-bit interval timer generates a count interrupt
15
The setting address of the DMABAR
register is +0FF
Timer40 ends with the count of channel 0 or
capture
16
The setting address of the DMABAR
register is +10H
Timer40 for channel 1 counts or captures end
17
The setting address of the DMABAR
register is +11H
Timer40 for channel 2 counts or snaps ends
18
The setting address of the DMABAR
register is +12H
Timer40 ends with the count or snap of channel 3
19
The setting address of the DMABAR
register is +13H
Timer41 ends counting or snapping of channel 0
20
The setting address of the DMABAR
register is +14H
Timer41 ends with the counting or snapping of
channel 1
21
The setting address of the DMABAR
register is +15H
Timer41 ends with the count or snap of channel 2
22
The setting address of the DMABAR
register is +16H
Timer41 ends with the counting or snapping of
channel 3
23
The setting address of the DMABAR
register is +17H
lo
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