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V1.2.2
CMS32L051 User Manual |Chapter 14 Serial interface IICA
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Figure 14-31 Example of a slave device master device
(Master device: select 9 clocks of waiting, slave device: select 9 clocks of waiting) (1/4)
(1) Start condition ~ address ~ data
slave address
AD0
AD5
AD6
W
master control
IICAn
ACKDn
（ACK
detection ）
WTIMn
(8 or 9 clock cycles
waiting)
H
ACKEn
（ACK
control ）
MSTSn
(communicdati
on state)
STTn
(ST trigger)
H
SPTn
(ST trigger)
L
WRELn
(release from
wait)
L
INTIICAn
（ interrupt ）
TRCn
（transmit
/reception）
Bus
SCLAn( bus )
（ Clock line ）
SDAAn( bus )
（ data line ）
slave
IICAn
ACKDn
（ACK detection ）
STDn
（ST detection ）
SPDn
（SP detection ）
WTIMn
(8 or 9 clock cycles
waiting)
ACKEn
（ACK control ）
MSTSn
(communicdation
state)
WRELn
(release from
wait)
TRCn
（transmit
/reception）
H
H
L
L
注2
start
condition
D17

Note3


Note1



：slave device waits
：master device and slave device wait
ACK
AD4 AD3
AD2
AD1
Note 1. To remove the wait during the master send, the IICAn must be written to the data instead of the set the WRELn
bit.
2. 
 mode.
3. To release the wait during the slave receive, the IICAn must be set to "FFH" or set the WRELn bit.