CMS32L051 User Manual |Chapter 14 Serial interface IICA
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Figure 14-31 (1) start condition ~ address ~ data (1) ~ (6) descriptions are as follows:
(1) If the start condition is triggered by the master (STTn=1), the bus data line (SDAAn) drops, generating
a start condition (changing SDAAn from 1 to 0 by SCLAn=1 ). Thereafter, if a start condition is detected,
the master enters the master communication state (MSTSn=1), and the bus clock line drops (SCLAn=0) after
the hold time elapses, ending the communication readiness.
(2) If the master parity writes address +W (send) to the IICA shift register n (IICAn), the slave address is
sent.
(3) On the slave side, if the receiving address and the local station address (the value of SVAn) are the
same, the ACK is sent to the master controller through the hardware. The master detected ACK (ACKDn=1)
on the rising edge of the 9th clock.
(4) The master generates an interrupt on the falling edge of the 9th clock (INTIICAn: address send end
interrupt). A slave of the same address enters a waiting state (SCLAn=0) and generates an interrupt
(INTIICAn: Address Matching Interrupt)
note
.
(5) The master writes and sends data to the IICAn register, relieving the master of waiting.
(6) If the slave unwaits (WRELn=1), the master begins to transmit data to the slave.
Note If the sending address and the slave address are different, the slave does not return an ACK (NACK: SDAAn=1) to
the master and does not generate an INTIICAn interrupt (address matching interrupt), nor does it enter a waiting
state.
However, the main controller generates an INTIICAn interrupt (address send end interrupt) for both ACK and
NACK.
Remark 1. Figure 14-31 ① to ⑮ shows a series of operational steps for data
communication via the I
2
C bus.
Figure 14-31 (1) start condition ~ address ~ data illustrates steps ①~⑥.
Figure 14-31 (2) address ~ data ~ data illustrates steps ③~⑩.
Figure 14-31 (3) data ~ data ~ stop conditions illustrates steps ⑦ ~ ⑮.
2. n=0
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