Cmsemicon CMS32L051 - Page 555

V1.2.2
CMS32L051 User Manual |Chapter 14 Serial interface IICA
www.mcu.com.cn 555 / 703
Figure 14-31 Communication example of a master device → slave device
(Master device: select 9 clocks of waiting, slave device: select 9 clocks of waiting) (2/4)
(2) Address ~ Data ~ Data



master control
IICAn
ACKDn
（ACK detection ）
WTIMn
(8 or 9 clock cycles
waiting)
H
ACKEn
（ACK control ）
MSTSn
(communicdati
on state)
STTn
(ST trigger)
H
SPTn
（SP trigger）
L
WRELn
（release from
wait）
L
INTIICAn
（ interrupt ）
TRCn
（transmit
/reception）
bus
SCLAn( bus )
（ Clock line）
SDAAn( bus )
（ data line）
slave
IICAn
ACKDn
（ACK detection）
STDn
（ST detection）
SPDn
（SP detection）
WTIMn
(8 or 9 clock cycles
waiting)
ACKEn
(ACK control)
MSTSn
(communicdati
on state)
WRELn
(release from
wait)
INTIICAn
（ interrupt ）
TRCn
（transmit
/reception）
H
H
L
L
D27

note 1

：slave device waits
：master device and slave device wait
H
L
note
1

H
W
D17
D16 D15
D14
ACK
D13
D12 D11
D10
L
note 2
note 2


ACK
Note 1. To release the master from waiting during transmit, you must write data to the IICAn instead of setting the
WRELn bit.
2. To release the slave from waiting during reception, the IICAn must be set to "FFH" or the WRELn bit must be set.