Cmsemicon CMS32L051 - Page 556

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CMS32L051 User Manual |Chapter 14 Serial interface IICA
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Figure 14-31 (2) address ~ data ~ data (3) ~ (10) of the descriptions are as follows:
(3) On the slave, if the receiving address and the local station address (the value of the SVAn) are the
same note, the ACK is sent to the master through the hardware. The master detects ACK on the rising edge of
the 9th clock (ACKDn=1).
(4) The master generates an interrupt on the falling edge of the 9th clock (INTIICAn: address send end
interrupt). Slaves with the same address enter a waiting state (SCLAn=0) and an interrupt (INTIICAn: address
matching interrupt)
Note
.
(5) The master writes the transmit data to the IICA shift register n (IICAn) to relieve the master 's wait.
(6) If the slave unwaits (WRELn=1), the master controller begins to transmit data to the slave.
(7) After the data transmission is completed, because the ACKEn bit of the slave party is 1, the ACK is
sent to the master controller through the hardware. The master detected ACK (ACKDn=1) on the rising edge
of the 9th clock.
(8) Both the master and slave enter a waiting state (SCLAn=0) on the falling edge of the 9th clock, and
both produce interrupts (INTIICAn: End of Transmission Interrupt).
(9) The main controller writes the transmitted data to the IICAn register and releases the main controller's
wait.
(10) If the slave reads the received data and unwaits (WRELn=1), the master controller begins to transmit
data to the slave.
Note If the sending address and the slave address are different, the slave does not return an ACK (NACK: SDAAn=1)
to the master and does not generate an INTIICAn interrupt (address matching interrupt), nor does it enter a
waiting state.
However, the main controller generates an INTIICAn interrupt (address send end interrupt) for both ACK and
NACK.
Note 1. Figure 14-31 ① to ⑮ shows a series of operational steps for data communication via the I2C bus.
Figure 14-31 (1) start condition ~ address ~ data illustrates steps (1) ~ (6).
Figure 14-31 (2) address ~ data ~ data illustrates steps (3) ~ (10).
Figure 14-31 (3) data ~ data ~ stop conditions illustrates steps (7) ~ (15)
2. n=0