CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4)
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Figure 5-71 Operation procedure for the PWM function (1/2)
Softeware operation Hardware status
Timer Unit m input clock is in stopped state (stop providing
clock, not able to write into registers)
set TM4mEN bit of peripheral enable register 0 (PER0) to '1'
Timer Unit m input clock is in active state, all channels in
operation stopped state.
configure Timer clock selection register m(TPSm), confirm
CKm0~CKm3 clock frequency
configure using timer mode register mn,mp (TMRmn,TMRmp)
of 2 channels (confirm channel operation mode).
Configure interal(period) value of Timer data register mn
(TDRmn) of master control channel, and configure duty-cycle
of slave channel TDRmp.
channel in operation stopped state
(providing clock, consume portion of power)
Channel Initial
configuration
Timer 4 initial
configuration
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