CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit
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(1) Register setting
Figure 12-104 Example of register settings when UART is received by UART (UART0~UART2) (1/2)
(a) serial mode register mn (SMRmn)
channel n operational clock (fMCK)
0: SPSm register configured pre-scaler output clock CKm0
1: SPSm register configured pre-scaler output clock CKm1
channel r operational mode:
0: transmit completion interrupt
1: buffer empty interrupt
channel N operational mode:
0: transmit completion interrupt
0: normal receiving
1: inverted phase receiving
(b) serial mode register mr(SMRmr)
samd configuration as CKSmn bit
data transmit sequence selection
0: perform MSB first input/output
1: perform LSB first input/output
data length configuration
parity check bit configuration
00B: no parity check
01B: add zero parity
10B: add even parity
11B: add odd parity
(d) serial data regsiter mn (SDRmn) (low 8 bit:TXDq)
TXDq
(c) serial communication operation configuration register mn(SCRmn)
baud rate configuration received data register
Note2
Note1
Note 1 Limited to SCR01 registers, other fixed as 1.
2. When communicating with a length of 9 bits of data, bit0 to 8 of the SDRm1 register is the setting area for sending
data. Only UART0 can communicate with 9-bit data lengths.
Notice When the UART is received, the SMRmr register of channel r paired with channel n must also be set.
Note 1. m: unit number (m=0, 1) n: channel number (n=1, 3) mn=01, 03, 11.
r: Channel number (r=n1) q: UART number (q=0~2)
2. : Fixed in UART receive mode. : Cannot be set (initial value).
×: This is the bit that cannot be used in this mode (set the initial value if it is not used in other modes either).
0/1: Set 0 or 1 according to the user's purpose.
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