Cmsemicon CMS32L051 - Page 48

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CMS32L051 User Manual |Chapter 2 Pin Function
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Table 2-12 Example of register settings when using P50 to P51 pin functions
Pin
name
Features used
PMCxx
PMx
x
Px
x
POMx
x
PxxCFG
(Output
Multiplexing
Configuration
Register)
xxPCFG (Input
Multiplexing
Configuration Register)
SPIPCFG
remark
The feature
name
Input/output
P50
P50
input
0
1
×
×
×
×
×
output
0
0
0/1
0

×
×
N-channel
open-drain
output
0
0
0/1
1
×
ANI23
Analog
channel
1
×
×
×
×
×
×
INTP1
input
0
1
×
×
×
×
×
INTP1 can also
be mapped to
other ports, see
2.3.9
VCOUT1
output
0
0
0
0

×
×
SPI_NSS
input
0
1
×
×
×
×

Please refer to
2.3.11
Mappable
concurrent
inputs
input
0
1
×
×
×
Configure xxPCFG
×
Please refer to
2.3.9
Mappable
concurrent
output
output
0
0
0/1
0
Configure the
P50CFG
×
×
Please refer to
2.3.10
Mappable
bidirectional
communicatio
n
(SDA00/SDAA
0/SCLA0)
bidirectional
0
0
0/1
1

Configure
SDI00PCFG/SDAA0PCF
G/SCLA0PCFG
×
Please refer to
2.3.9
P51
P51
input
0
1
×
×
×
×
×
output
0
0
0/1
0

×

N-channel
open-drain
output
0
0
0/1
1

ANI24
Analog
channel
1
×
×
×
×
×
×
INTP2
input
0
1
×
×
×
×
×
INTP2 can also
be mapped to
other ports, see
2.3.9
SPI_SCK
input
0
1
×
×
×
×

Please refer to
2.3.11
output
0
0
0
0
×
×
Mappable
concurrent
inputs
input
0
1
×
×
×
Configure xxPCFG
×
Please refer to
2.3.9
Mappable
concurrent
output
output
0
0
0/1
0
Configure the
P51CFG
×

Please refer to
2.3.10
Mappable
bidirectional
communicatio
n
(SDA00/SDAA
0/SCLA0)
bidirectional
0
0
0/1
1

Configure
SDI00PCFG/SDAA0PCF
G/SCLA0PCFG

Please refer to
2.3.9