CMS32L051 User Manual |Chapter 14 Serial interface IICA
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Table 14-4 Status of the arbitration and the timing of the interrupt request
Status at the time arbitration occurred
Timing of the interrupt request
The address is sent during the sending process
On the falling edge of the 8th or 9th clock after byte transfer
Note 1
Read and write information after sending the address
During the sending of extension codes
Read and write information after sending the extension
code
During the delivery of the reply after the data is sent
A restart condition was detected during data transfer.
A stop condition was detected during data transfer.
When generating the stop condition (SPIEn=1)
Note 2
.
You want to generate a restart condition, but the data is
low.
On the falling edge of the 8th or 9th clock after byte transfer
Note 1
You want to generate a restart condition, but a stop
condition is detected.
When generating the stop condition (SPIEn=1)
Note 2
.
You want to generate a stop condition, but the data is low.
On the falling edge of the 8th or 9th clock after byte transfer
Note 1
You want to generate a restart condition, but SCLAn is low.
Note 1. When WTIMn bit (bit 3 of IICA control register n0 (IICCTLn0)) is "1", an interrupt request is generated on the
falling edge of the 9th clock; when WTIMn bit is "0" and the slave address of the extension code is received, an
interrupt request is generated on the falling edge of the 8th clock.
2. When arbitration is possible, the SPIEn bit must be set to "1" when the master is running.
Note 1. SPIEn: Bit4 of the IICA control register n0 (IICCTLn0).
2. n=0
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