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CMS32L051 User Manual |Chapter 14 Serial interface IICA
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Figure 14-28 Master operation of multi-master systems (3/3)
communication process
C
Write IICAn
Start communication.
(Specify address and transfer
direction)
does INTIICAn interrupt
occur?
wait for detecing
acknowledgement
No
Yes
MSTSn=1？
Yes
ACKDn=1？
TRCn=1？
WTIMn=1
Write IICAn
does INTIICAn interrupt
occur?
wait for transmitting
data
No
Yes
MSTSn=1？
Yes
ACKDn=1？
start transmission
Yes
2
No
Yes
Yes
transmission completes?
restart?
Yes
Yes
STTn=1
C
SPTn=1
END
No
No
2
No
ACKEn=1
WTIMn=0
WRELn=1
does INTIICAn interrupt
occur?
wait for receiving
data
No
MSTSn=1？
2
No
Yes
Read IICAn
transmission completes?
start
receiving
Yes
Yes
ACKEn=0
WTIMn=1
WRELn=1
does INTIICAn interrupt
occur?
No
MSTSn=1？
2
No
Yes
Yes
wait for detecing
acknowledgement
No
2
EXCn=1 or COIn=1?
slave operation
Yes
1
No
does not participant
communication
communication process
No
Note 1. The format of transmission and reception must conform to the specifications of the product in the communication.
2. In the case of being used as a master device in a multi-master system, the MSTSn bit must be read every time an
INTIICAn interruption occurs to confirm the arbitration result.
3. In the case of use as a slave device in a multi-master system, the IICA status register n (IICSn) and IICA flag
registers must be passed every time an INTIICAn interrupt occurs n (IICFn) confirms the status and decides on
future processing.
4. n=0