CMS32L051 User Manual |Chapter 14 Serial interface IICA
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The description of ⑧~⑲ of "(3) Data - Data - Stop condition" in Fig. 16-32 is as follows:
⑧. The master enters a waiting state (SCLAn=0) on the falling edge of the 8th clock and generates an
interrupt (INTIICAn: End of Transmission Neutral). Since the ACKEn bit of the master is 0, the
ACK is sent to the slave through the hardware.
⑨. The master receiver reads the received data and unwaits (WRELn=1).
⑩. The slave detected an ACK (ACKDn=1) on the rising edge of the 9th clock.
⑪. The slave enters a waiting state (SCLAn=0) on the falling edge of the 9th clock and generates an
interrupt (INTIICAn: transmit end interrupt).
⑫. If the slave writes the send data to the IICA shift register n (IICAn), the slave is relieved of the wait
and the data transfer from the slave to the master controller begins.
⑬. The master generates an interrupt on the falling edge of the 8th clock (INTIICAn: transmit end
interrupt) and enters a waiting state (SCLAn=0). Because of the ACK control (ACKEn=1), the bus
data line at this stage becomes low (SDAAn=0).
⑭. The master sets the NACK Acknolwdge (ACKEn=0) and changes the wait sequence to the 9th
clock (WTIMn=1). If the master relieshes the wait (WRELn=1), the slave detects THEACK
(ACKDn=0) on the rising edge of the 9th clock.
⑮. Both the master and slave enter a waiting state (SCLAn=0) on the falling edge of the 9th clock and
both generate interrupts (INTIICAn: End of Transmission Interrupt).
⑯. If the master issues a stop condition (SPTn=1), the bus data cable (SDAAn=0) is cleared and the
master's wait is released. Thereafter, the master is in standby until the bus clock line is asserted
(SCLAn=1).
⑰. The slave stops sending after acknowledging the NACK, and in order to end the communication,
the wait is released (WRELn=1). If the slave is relieved of waiting, the bus clock line is set
(SCLAn=1).
⑱. If the master confirms that the bus clock line is being set (SCLAn=1), the bus data line is set after
the stop condition preparation time has elapsed
⑲. (SDAAn=1), and then issue a stop condition (change SDAAn from 0 to 1 by SCLAn=1). If a stop
condition is generated, the slave detects the stop condition and generates an interrupt (INTIICAn:
Stop condition interrupt).
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