Cmsemicon CMS32L051 - Page 590

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CMS32L051 User Manual |Chapter 16 Enhanced DMA
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DMAENi2
DMA boot enable i2
0
Disable startup.
1
Enable startup.
Depending on the condition under which the end-of-transmission interrupt occurs, the DMAENi2 bit
becomes 0 (disable start).
DMAENi1
DMA boot enable i1
0
Disable startup.
1
Enable startup.
Depending on the conditions under which the end-of-transmission interrupt occurs, the DMAENi1 bit
becomes 0 (disable start).
DMAENi0
DMA boot enable i0
0
Disable startup.
1
Enable startup.
Depending on the condition under which the end-of-transmission interrupt occurs, the DMAENi0 bit
becomes 0 (disable start-up).
Table 16-6 Interrupt source corresponds to DMAENi0~DMAENi7 bits
register
DMAENi 7 bits
DMAENi 6 bits
DMAENi 5 bits
DMAENi 4 bit
DMAENi 3 bits
DMAENi 2 bits
DMAENi 1 bit
DMAENi0 bit
DMAEN0
retain
retain
The A/D
conversion
ends
INTP3
INTP2
INTP1
INTP0
Flash
erase/write
ends
DMAEN1
15-bit interval
timer interrupt
IICA0
communicatio
n ends
The end of the
UART2
transmission /
the end of the
SSPI20
transmission
or the end of
the buffer
null/IIC20
transmission
The end of
transmission
received by
UART2 / the
end of
transmission
of SSPI21 or
the end of
transmission
of buffer
NULL/IIC21
End of
transmission
for UART1
transmission/e
nd of
transmission
for SSPI10 or
end of
transmission
for buffer
NULL/IIC10/e
nd of
transmission
for SPI
The end of
transmission
received by
UART1 / the
end of
transmission
of SSPI11 or
the end of
transmission
of buffer
NULL/IIC11
The end of the
UART0
transmission /
the end of the
SSPI00
transmission
or the end of
the buffer
NULL/IIC00
transmission
The end of
transmission
received by
UART0 / the
end of
transmission
of SSPI01 or
the end of
transmission
of buffer
NULL/IIC01
DMAEN2
The counting
end of
channel 3 of
the timer array
unit 1 ends or
the capture
ends
The counting
end of
channel 2 of
the timer array
unit 1 ends or
the capture
ends
The counting
end of
channel 1 of
timer array
unit 1 or the
end of the
snap
The counting
end of
channel 0 of
timer array
unit 1 ends or
the snap ends
The counting
end of
channel 3 of
the timer array
unit 0 or the
end of the
snap
The counting
end of
channel 2 of
timer array
unit 0 ends or
the snap ends
The counting
end of
channel 1 of
the timer array
unit 0 ends or
the capture
ends
The counting
end of channel
0 of the timer
array unit 0
ends or the
snap ends
Note Bits that are not assigned a function must be set to "0".
Note i=0~2