CMS32L051 User Manual |Chapter 16 Enhanced DMA
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(1) Example 1 of the use of normal mode: Continuous A/D conversion results
DMA is started by an A/D conversion end interrupt, and the value of the A/D conversion result register is
transferred to RAM.
The vector address is allocated at 200,00005H, and the control data is distributed at 20000070
H~20000007FH.
20000400H~of RAM 2000044FH 80 bytes.
Figure 16-16 Normal mode usage example 1: Continuously take the A/D conversion result
DMABAR=20000000H
vector address (20000005H)=05H
DMACR10(20000070H)=0048H
DMBLS10(20000072H)=0001H
DMACT10(20000074H)=0028H
DMSAR10(20000078H)=40045004H
DMDAR10(2000007CH)=20000400H
DMAEN0=20H
start A/D conversion
A/D conversion completion interrupt?
Yes
DMACT10=01H？
No
data transmit
No
generate A/D conversion completion interrupt
request
DMAEN0=00H
data transmit
interrupt handling
Yes
internal handling automatically executed by DMA
RAM
A/D conversion result register
20000400H
2000044EH
Because it is in normal mode, the value of the DMRLD10 register is not used. However, when parity
error reset (RPERDIS=0) is allowed to occur via the RAM parity error detection function, the DMRLD10
register must be initialized (0000H).
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