Cmsemicon CMS32L051 - Page 597

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CMS32L051 User Manual |Chapter 16 Enhanced DMA
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Figure 16-18 Data transfer in repeat mode
DMACTj register 
FFFFFFFFH
1The second boot to be delivered
The data block size (N bytes).
DMBLSj register = N
DMACTj register 
DMSARj register =
SRC
DMDARj register =
DST
j=0~23
00000000H
The setting of the DMACR register
Control of the
source address
Control of the
destination
address
The source
address after
transmission
The destination
address after
transmission
DAMOD
SAMOD
RPTSEL
MODE
0
X
1
1
Repeating area
fixed
SRC+N
Dst
1
X
1
1
Repeating area
Increasing
SRC+N
DST+N
X
0
0
1
fixed
Repeating area
SRC
DST+N
X
1
0
1
Increasing
Repeating area
SRC+N
DST+N
X: 0 or 1
DMACTj register = 1
FFFFFFFFH
DMBLSj register = N
DMACTj register = 1
DMSARj register =
SRC
DMDARj register =
DST
j=0~23
00000000H
The setting of the DMACR register
Control of the
source address
Control of the
destination address
The source address
after transmission
The destination
address after
transmission
DAMOD
SAMOD
RPTSEL
MODE
0
X
1
1
Repeating area
fixed
SRC
Dst
1
X
1
1
Repeating area
Increasing
SRC
DST+N
X
0
0
1
fixed
Repeating area
SRC
Dst
X
1
0
1
Increasing
Repeating area
SRC+N
Dst
X: 0 or 1
Note 1 When using repeat patterns, the data length of the repeat must be set to less than 65535 bytes.