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CMS32L051 User Manual |Chapter 18 Interrupt Function
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18.3.3 External interrupt rising edge enable register (EGP0), External interrupt falling edge
enable register (EGN0)
These registers set the effective edges of INTP0 to INTP3.
Set the EGP0 and EGN0 registers via 8-bit memory operation instructions.
After the reset signal is generated, the values of these registers become 00H.
Figure 18-5 Format of external interrupt rising edge enable register (EGP0), external interrupt falling edge
enable register (EGN0)
Address: 40045B38H After reset: 00HR/W
symbol
7
6
5
4
3
2
1
0
EGP0
0
0
0
0
EGP3
EGP2
EGP1
EGP0
Address: 40045B39H after reset: 00HR/W
symbol
7
6
5
4
3
2
1
0
EGN0
0
0
0
0
EGN3
EGN2
EGN1
EGN0
EGPn
EGNn
Valid edge selection for the INTPn pin (n=0~11)
0
0
Disable detection of edges.
0
1
Falling edge
1
0
Rising edge
1
1
Rising and falling edges
The ports corresponding to the EGPn bit and the EGNn bit are shown in Table 18-3.