Real-time clock (RTC) RM0453
1026/1461 RM0453 Rev 1
Note: Bits 6 and 4 of this register can be written in initialization mode only (RTC_ICSR/INITF = 1).
WUT = wakeup unit counter value. WUT = (0x0000 to 0xFFFF) + 0x10000 added when
WUCKSEL[2:1 = 11].
Bits 2 to 0 of this register can be written only when RTC_CR WUTE bit = 0 and RTC_ICSR
WUTWF bit = 1.
It is recommended not to change the hour during the calendar hour increment as it could
mask the incrementation of the calendar hour.
ADD1H and SUB1H changes are effective in the next second.
Bit 7 SSRUIE: SSR underflow interrupt enable
0: SSR underflow interrupt disabled
1: SSR underflow interrupt enabled
Bit 6 FMT: Hour format
0: 24 hour/day format
1: AM/PM hour format
Bit 5 BYPSHAD: Bypass the shadow registers
0: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from
the shadow registers, which are updated once every two RTCCLK cycles.
1: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken
directly from the calendar counters.
Note: If the frequency of the APB1 clock is less than seven times the frequency of RTCCLK,
BYPSHAD must be set to 1.
Bit 4 REFCKON: RTC_REFIN reference clock detection enable (50 or 60 Hz)
0: RTC_REFIN detection disabled
1: RTC_REFIN detection enabled
Note: BIN must be 0x00 and PREDIV_S must be 0x00FF.
Bit 3 TSEDGE: Timestamp event active edge
0: RTC_TS input rising edge generates a timestamp event
1: RTC_TS input falling edge generates a timestamp event
TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting.
Bits 2:0 WUCKSEL[2:0]: ck_wut wakeup clock selection
000: RTC/16 clock is selected
001: RTC/8 clock is selected
010: RTC/4 clock is selected
011: RTC/2 clock is selected
10x: ck_spre (usually 1 Hz) clock is selected in BCD mode. In binary or mixed mode, this is
the clock selected by BCDU.
11x: ck_spre (usually 1 Hz) clock is selected in BCD mode. In binary or mixed mode, this is
the clock selected by BCDU. Furthermore, 2
16
is added to the WUT counter value.
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