RM0453 Rev 1 993/1461
RM0453 System window watchdog (WWDG)
997
31.3.1 WWDG block diagram
Figure 271. Watchdog block diagram
31.3.2 WWDG internal signals
Table 205 gives the list of WWDG internal signals.
31.3.3 Enabling the watchdog
The watchdog is always disabled after a reset. It is enabled by setting the WDGA bit in the
WWDG_CR register, then it cannot be disabled again except by a reset.
31.3.4 Controlling the down-counter
This down-counter is free-running, counting down even if the watchdog is disabled. When
the watchdog is enabled, the T6 bit must be set to prevent generating an immediate reset.
The T[5:0] bits contain the number of increments that represent the time delay before the
watchdog produces a reset. The timing varies between a minimum and a maximum value
due to the unknown status of the prescaler when writing to the WWDG_CR register (see
Figure 272). The WWDG configuration register (WWDG_CFR) contains the high limit of the
window: to prevent a reset, the down-counter must be reloaded when its value is lower than
the window register value and greater than 0x3F. Figure 272 describes the window
watchdog process.
MS47214V1
7-bit DownCounter (CNT)
WWDG
pclk
APB bus
÷ 4096 ÷ 2
WDGTB
Write to WWDG_CR
CMP = 1 when
T[6:0] > W[6:0]
CMP
T[6:0]
preload
WWDG_CR
wwdg_out_rst
wwdg_it
= 0x40 ?
readback
WWDG_CFR
W[6:0]
cnt_out
Register interface
WWDG_SR
T6
T[6:0]
WDGA
EWI
Logic
EWIF
Table 205. WWDG internal input/output signals
Signal name Signal type Description
pclk Digital input APB bus clock
wwdg_out_rst Digital output WWDG reset signal output
wwdg_it Digital output WWDG early interrupt output
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