Digital-to-analog converter (DAC) RM0453
602/1461 RM0453 Rev 1
The sample/hold mode operations can be divided into 3 phases:
1. Sample phase: the sample/hold element is charged to the desired voltage. The
charging time depends on capacitor value (internal or external, selected by the user).
The sampling time is configured with the TSAMPLE1[9:0] bits in DAC_SHSR1 register.
During the write of the TSAMPLE1[9:0] bits, the BWST1 bit in DAC_SR register is set
to 1 to synchronize between both clocks domains (APB and low speed clock) and
allowing the software to change the value of sample phase during the DAC channel
operation
2. Hold phase: the DAC output channel is tri-stated, the DAC core and the buffer are
turned off, to reduce the current consumption. The hold time is configured with the
THOLD1[9:0] bits in DAC_SHHR register
3. Refresh phase: the refresh time is configured with the TREFRESH1[7:0] bits in
DAC_SHRR register
The timings for the three phases above are in units of LSI clock periods. As an example, to
configure a sample time of 350 µs, a hold time of 2 ms and a refresh time of 100 µs
assuming LSI ~32 KHz is selected:
12 cycles are required for sample phase: TSAMPLE1[9:0] = 11,
62 cycles are required for hold phase: THOLD1[9:0] = 62,
and 4 cycles are required for refresh period: TREFRESH1[7:0] = 4.
In this example, the power consumption is reduced by almost a factor of 15 versus Normal
modes.
The formulas to compute the right sample and refresh timings are described in the table
below, the Hold time depends on the leakage current.
Example of the sample and refresh time calculation with output buffer on
The values used in the example below are provided as indication only. Please refer to the
product datasheet for product data.
C
SH
= 100 nF
V
DD
= 3.0 V
Sampling phase:
t
SAMP
= 7 μs + (10 * 2000 * 100 * 10
-9
) = 2.007 ms
(where R
BON
= 2 kΩ)
Table 115. Sample and refresh timings
Buffer
State
t
SAMP
(1)(2)
1. In the above formula the settling to the desired code value with ½ LSB or accuracy requires 10 constant
time for 12 bits resolution. For 8 bits resolution, the settling time is 7 constant time.
2. C
SH
is the capacitor in Sample and hold mode.
t
REFRESH
(2)(3)
3. The tolerated voltage drop during the hold phase “Vd” is represented by the number of LSBs after the
capacitor discharging with the output leakage current. The settling back to the desired value with ½ LSB
error accuracy requires ln(2*Nlsb) constant time of the DAC.
Enable 7 μs + (10*R
BON
*C
SH
)7μs + (R
BON
*C
SH
)*ln(2*N
LSB
)
Disable 3 μs + (10*R
BOFF
*C
SH
)3μs + (R
BOFF
*C
SH
)*ln(2*N
LSB
)
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