Embedded Flash memory (FLASH) RM0453
100/1461 RM0453 Rev 1
After power-on reset and wakeup from Standby, the HCLK3 clock frequency is 4 MHz in
range 1 and 0 wait state (WS) is configured in FLASH_ACR.
When changing the frequency of the Flash memory clock or the V
CORE
range, the software
sequences detailed below must be applied in order to tune the number of wait states
needed to access the Flash memory:
Increase the CPU frequency
1. Program the new number of wait states to the LATENCY[2:0] bits in FLASH_ACR.
2. Check that the new number of wait states is taken into account to access the Flash
memory by reading back the LATENCY[2:0] bits in FLASH_ACR, and wait until the new
programmed number is read.
3. Modify the system cock source by writing the SW[1:0] bits in RCC_CFGR.
4. If needed, modify the CPU clock prescaler by writing the SHDHPRE[3:0] bits in
RCC_EXTCFGR.
5. Optionally, check that the new system clock source or/and the new Flash memory clock
prescaler value is/are taken into account by reading the clock source status (SWS(1:0]
bits) in RCC_CFGR, or/and the AHB prescaler value (SHDHPREF bit) in
RCC_EXTCFGR.
Decrease the CPU frequency
1. Modify the system clock source by writing the SW[1:0] bits in RCC_CFGR.
2. If needed, modify the Flash memory clock prescaler by writing the SHDHPRE[3:0] bits
in RCC_EXTCFGR.
3. Check that the new system clock source or/and the new Flash memory clock prescaler
value is/are taken into account by reading the clock source status (SWS[1:0] bits) in
RCC_CFGR, or/and the AHB prescaler value (SHDHPREF bit) in RCC_EXTCFGR.
Wait until the new programmed system clock source or/and new Flash memory clock
prescaler value is/are read.
4. Program the new number of wait states to the LATENCY[2:0] bits in FLASH_ACR.
5. Optionally, check that the new number of wait states is used to access the Flash
memory by reading back the LATENCY[2:0] bits in FLASH_ACR.
4.3.5 Adaptive real-time memory accelerator (ART Accelerator)
The proprietary adaptive real-time (ART) memory accelerator is optimized for STM32
industry-standard Arm
Cortex-M4 with DSP processors. It balances the inherent
performance advantage of the Cortex-M4 with DSP over Flash memory technologies, which
normally require the processor to wait for the Flash memory at higher operating frequencies.
To release the processor full performance, the accelerator implements an instruction
prefetch queue and branch cache that increases program execution speed from the 64-bit
Flash memory. Based on CoreMark
®
benchmark, the performance achieved thanks to the
ART Accelerator is equivalent to 0 wait state program execution from the Flash memory at a
CPU frequency up to 48 MHz.
Instruction prefetch
The CPU1 fetches the instruction over the ICode bus and the literal pool (constant/data)
over the DCode bus. The prefetch block aims at increasing the efficiency of ICode bus
accesses.
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